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參數(shù)資料
| 型號(hào)： | MC10133 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Quad Latch |
| 中文描述： | 四鎖存 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大小： | 85K |
| 代理商： | MC10133 |
MC10133
3–15
MOTOROLA
MECL Data
DL122 — Rev 6
ELECTRICAL CHARACTERISTICS
(continued)
TEST VOLTAGE VALUES
(Volts)
@ Test Temperature
VIHmax
–0.890
VILmin
–1.890
VIHAmin
–1.205
VILAmax
–1.500
VEE
–5.2
–30
°
C
+25
°
C
–0.810
–1.850
–1.105
–1.475
–5.2
+85
°
C
–0.700
–1.825
–1.035
–1.440
–5.2
Pin
Under
Test
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(VCC)
Gnd
Characteristic
Symbol
VIHmax
VILmin
13
VIHAmin
VILAmax
VEE
8
Power Supply Drain Current
IE
IinH
8
1, 16
Input Current
3
4
5
13
3
4
5
13
8
8
8
8
1, 16
1, 16
1, 16
1, 16
IinL
VOH
3
3
8
1, 16
Output Voltage
Logic 1
2
2
3, 4
3, 13
8
8
1, 16
1, 16
Output Voltage
Logic 0
VOL
2
2
2
13
3, 5, 13
4
3
3
8
8
8
1, 16
1, 16
1, 16
Threshold Voltage
Logic 1
VOHA
2
2
2
2
2
2
2
2
3, 4
4
3, 4
3
3
3
3
4
13
5
4
8
8
8
8
8
8
8
8
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
Threshold Voltage
Logic 0
VOLA
2
2
2
2
2
2
3, 4
4
4
3
3
5
3
13
8
8
8
8
8
8
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
Switching Times
(50
Load)
+1.11V
Pulse In
Pulse Out
–3.2 V
+2.0 V
Propagation Delay
t3+2+
t4+2+
t5–2+
tsetup
thold
t2+
t2–
2
2
2
3
3
4
3*
3
4
5
3
3
2
2
2
2
2
8
8
8
8
8
1, 16
1, 16
1, 16
1, 16
1, 16
Rise Time
(20 to 80%)
2
4
3
2
8
1, 16
Fall Time
(20 to 80%)
2
4
3
2
8
1, 16
Output level to be measured after a clock pulse has been applied to the clock input (Pin 4)
VIHmax
VILmin
Data input at proper high/low level while clock pulse is high so that device latches ar proper high/low level for test. Levels are measured after
device has latched.
* Latch set to zero state before test.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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