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參數(shù)資料
| 型號： | MC10101FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual J-K Flip-Flops With Clear 14-CDIP -55 to 125 |
| 中文描述： | 10K SERIES, QUAD 1-INPUT INV/NINV GATE, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 100K |
| 代理商： | MC10101FN |
SEMICONDUCTOR TECHNICAL DATA
3–1
REV 5
Motorola, Inc. 1996
3/93
The MC10101 is a quad 2–input OR/NOR gate with one input from
each gate common to pin 12.
PD= 25 mW typ/gate (No Load)
tpd= 2.0 ns typ
tr, tf= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
VCC1= PIN 1
VCC2= PIN 16
VEE= PIN 8
12
9
13
10
7
4
15
11
14
6
3
5
2
DIP
PIN ASSIGNMENT
VCC1
AOUT
BOUT
AIN
AOUT
BOUT
BIN
VEE
VCC2
DOUT
COUT
DIN
COMMON
INPUT
COUT
CIN
DOUT
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–36 of the Motorola MECL Data
Book (DL122/D).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC10101 | Quad OR/NOR Gate |
| MC10101L | Dual J-K Flip-Flops With Clear 14-CDIP -55 to 125 |
| MC10101P | Dual J-K Flip-Flops With Clear 14-CDIP -55 to 125 |
| MC10102FN | Quad 2-Input NOR Gate |
| MC10102 | Quad 2-Input NOR Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC10101FN WAF | 制造商:ON Semiconductor 功能描述: |
| MC10101FNR2 | 制造商:ON Semiconductor 功能描述:OR/NOR Gate 4-Element 2-IN ECL 20-Pin PLLC T/R 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC10101L | 制造商:ON Semiconductor 功能描述:OR/NOR Gate 4-Element 2-IN ECL 16-Pin CDIP Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC10101L1 | 制造商:Motorola Inc 功能描述:10101L1 |
| MC10101LDS | 制造商:Motorola Inc 功能描述:Logic Circuit, 4 2-Input OR/NOR, 16 Pin, Ceramic, DIP |
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