VEE V
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MC100LVEP16DG
寤犲晢锛� ON Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 5/12闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC RECEIVER/DRVR ECL DIFF 8SOIC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 98
绯诲垪锛� 100LVEP
閭忚集椤炲瀷锛� 宸垎鎺ユ敹鍣�/椹�(q奴)鍕曞櫒
闆绘簮闆诲锛� 2.375 V ~ 3.8 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-SOICN
鍖呰锛� 绠′欢
鍏跺畠鍚嶇ū锛� MC100LVEP16DGOS
MC10LVEP16, MC100LVEP16
http://onsemi.com
2
1
2
3
45
6
7
8
Q
VEE
VCC
D
Q
D
VBB
NC
Figure 1. 8Lead Pinout (Top View) and Logic
Diagram
Table 1. PIN DESCRIPTION
Pin
Function
D*, D**
ECL Data Inputs
Q, Q
ECL Data Outputs
VBB
Ref. Voltage Output
VCC
Positive Supply
VEE
Negative Supply
NC
No Connect
EP
(DFN8 only) Thermal exposed pad must
be connected to a sufficient thermal con-
duit. Electrically connect to the most neg-
ative supply (GND) or leave unconnec-
ted, floating open.
* Pins will default LOW when left open.
**Pins will default to VCC/2 when left open.
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
37.5 kW
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Level 1
Flammability Rating Oxygen Index: 28 to 34
UL 94 V0 @ 0.125 in
Transistor Count
167 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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