- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358131 > MC100LVEL38DWG (ON SEMICONDUCTOR) 3.3V ECL ±2, ±4/6 Clock Generation Chip PDF資料下載
參數(shù)資料
| 型號(hào)： | MC100LVEL38DWG |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V ECL ±2, ±4/6 Clock Generation Chip |
| 中文描述： | 100LVEL SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | LEAD FREE, SOIC-20 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 219K |
| 代理商： | MC100LVEL38DWG |
Semiconductor Components Industries, LLC, 2008
November, 2008
Rev. 10
1
Publication Order Number:
MC100LVEL38/D
MC100LVEL38
3.3VECL
÷
2,
÷
4/6 Clock
Generation Chip
Description
The MC100LVEL38 is a low skew
÷
2,
÷
4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either a
differential or single-ended input signal.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as can happen with an
asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
The Phase_Out output will go HIGH for one clock cycle whenever
the
÷
2 and the
÷
4/6 outputs are both transitioning from a LOW to a
HIGH. This output allows for clock synchronization within the system.
Upon startup, the internal flip-flops will attain a random state; therefore,
for systems which utilize multiple LVEL38s, the master reset (MR) input
must be asserted to ensure synchronization. For systems which only use
one LVEL38, the MR pin need not be exercised as the internal divider
design ensures synchronization between the
÷
2 and the
÷
4/6 outputs of a
single device.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
50 ps Maximum Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
ESD Protection: >2 kV Human Body Model
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range:
V
CC
= 3.0 V to 3.8 V with V
EE
= 0 V
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
=
3.0 V to
3.8 V
Internal Input 75 k Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
Moisture Sensitivity Pb = Level 1
Pb
Free = Level 3
For Additional Information, see Application Note
AND8003/D
Flammability Rating: UL 94 V
0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 388 devices
Pb
Free Packages are Available*
*For additional information on our Pb
Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
*For additional marking information, refer to
Application Note AND8002/D.
MARKING DIAGRAM*
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb
Free Package
SO
20 WB
DW SUFFIX
CASE 751D
20
1
100LVEL38
AWLYYWWG
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC100LVEL38DWR2 | 3.3V ECL ±2, ±4/6 Clock Generation Chip |
| MC100LVEL38DWR2G | 3.3V ECL ±2, ±4/6 Clock Generation Chip |
| MC100LVEL39DWG | 3.3V ECL ±2/4, ±4/6 Clock Generation Chip |
| MC100LVEL39DWR2 | 3.3V ECL ±2/4, ±4/6 Clock Generation Chip |
| MC100LVEL39DWR2G | 3.3V ECL ±2/4, ±4/6 Clock Generation Chip |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100LVEL38DWR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V ECL Clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MC100LVEL38DWR2G | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V ECL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MC100LVEL39DW | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V ECL Clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MC100LVEL39DWG | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V ECL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MC100LVEL39DWR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V ECL Clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。