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參數(shù)資料
| 型號： | MC100LVEL34DTG |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V ECL ±2, ±4, ±8 Clock Generation Chip |
| 中文描述： | 100LVEL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | LEAD FREE, TSSOP-16 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 153K |
| 代理商： | MC100LVEL34DTG |
Semiconductor Components Industries, LLC, 2006
November, 2006
Rev. 2
1
Publication Order Number:
MC100LVEL34/D
MC100LVEL34
3.3VECL
÷
2,
÷
4,
÷
8 Clock
Generation Chip
Description
The MC100LVEL34 is a low skew
÷
2,
÷
4,
÷
8 clock generation
chip designed explicitly for low skew clock generation applications.
The internal dividers are synchronous to each other, therefore, the
common output edges are all precisely aligned. The V
BB
pin, an
internally generated voltage supply, is available to this device only.
For single
ended input conditions, the unused differential input is
connected to V
BB
as a switching reference voltage. V
BB
may also
rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a
0.01 F capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
BB
should be left open.
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip-flop is clocked on the falling edge of
the input clock; therefore, all associated specification limits are
referenced to the negative edge of the clock input.
Upon start
up, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple LVEL34s in a system.
Features
50 ps Typical Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
1.5 GHz Toggle Frequency
The 100 Series Contains Temperature Compensation.
PECL Mode Operating Range:
V
CC
= 3.0 V to 3.8 V with V
EE
= 0 V
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
=
3.0 V to
3.8 V
Open Input Default State
LVDS Input Compatible
Pb
Free Packages are Available
SO
16
D SUFFIX
CASE 751B
1
16
MARKING
DIAGRAMS*
A
L, WL
Y
W, WW = Work Week
G or
= Pb
Free Package
(Note: Microdot may be in either location)
= Assembly Location
= Wafer Lot
= Year
1
16
100LVEL34G
AWLYWW
1
16
TSSOP
16
DT SUFFIX
CASE 948F
VL34
ALYW
100
1
16
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
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PDF描述 |
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| MC100LVEL34DTR2 | 3.3V ECL ±2, ±4, ±8 Clock Generation Chip |
| MC100LVEL34DTR2G | 3.3V ECL ±2, ±4, ±8 Clock Generation Chip |
| MC10H130 | Dual Latch |
| MC10H130FNG | Dual Latch |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100LVEL34DTR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3V ECL Clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MC100LVEL34DTR2G | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3V ECL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MC100LVEL37DW | 功能描述:時鐘驅(qū)動器及分配 3.3V ECL Clock RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100LVEL37DWG | 功能描述:時鐘驅(qū)動器及分配 3.3V ECL Clock Fanout Buffer RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100LVEL37DWR2 | 功能描述:時鐘驅(qū)動器及分配 3.3V ECL Clock RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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