參數(shù)資料
型號(hào): MC100ES7014DT
廠(chǎng)商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 時(shí)鐘及定時(shí)
英文描述: 100E SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封裝: PLASTIC, TSSOP-20
文件頁(yè)數(shù): 4/5頁(yè)
文件大?。?/td> 108K
代理商: MC100ES7014DT
MC100ES7014
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
753
Table 6. AC Characteristics (VCC = 3.3V±5%; TJ = 0°C to 110°C)
1 2
1.
AC characteristics are design targets and pending characterization.
2.
AC characteristics apply for parallel output termination of 50
to V
TT.
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
HSTL/LVDS differential input signals (CLK0, CLK0)
VDIF
Differential Input Voltage (peak-to-peak)3
3.
VDIF (AC) is the minimum differential HSTL/LVDS input voltage swing required to maintain AC characteristics including tpd and device-to-device
skew.
0.4
V
VX, IN
Differential Cross Point Voltage4
4.
VX (AC) is the crosspoint of the differential HSTL/LVDS input signal. Functional operation is obtained when the crosspoint is within the VX (AC)
range and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF(AC) impacts the device propagation delay, device
and part-to-part skew.
0.68
1.275
V
fCLK
Input Frequency
1000
TBD
MHz
Differential
tPD
Propagation Delay
TBD
ps
Differential
PECL differential input signals (CLK1, CLK1)
VPP
Differential Input Voltage (peak-to-peak)5
5.
VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew.
0.2
1.0
V
VCMR
Differential Cross Point Voltage6
6.
VCMR (AC) is the crosspoint of the differential PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC)
range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP(AC) impacts the device propagation delay, device
and part-to-part skew.
1VCC – 0.6
V
fCLK
Input Frequency
1000
MHz
Differential
tPD
Propagation Delay
TBD
ps
Differential
LVDS clock outputs (Q[0:4], Q[0:4])
tSK(O)
Output-to-Output Skew
50
ps
Differential
tSK(PP)
Output-to-Output Skew (part-to-part)
TBD
ps
Differential
tJIT(CC)
Output Cycle-to-Cycle Jitter
TBD
DCO
Output Duty Cycle
TBD
50
TBD
%
DCfref = 50%
tr / tf
Output Rise/Fall Times
0.05
TBD
ns
20% to 80%
tPDL
Output Disable Time7
7.
Propagation delay EN deassertion to differential output disabled (differential low: true output low, complementary output high).
2.5*T +tPD
3.5*T +tPD
ns
T = CLK period
tPLD
Output Enable Time8
8.
Propagation delay EN assertion to output enabled (active).
3*T +tPD
4*T +tPD
ns
T = CLK period
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