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參數資料
| 型號： | MC100ES6226AC |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | LEAD FREE, PLASTIC, LQFP-32 |
| 文件頁數： | 6/9頁 |
| 文件大小： | 642K |
| 代理商： | MC100ES6226AC |
IDT / ICS CLOCK DISTRIBUTION BUFFER/CLOCK DRIVER
6
MC100ES6226 REV. 5 NOVEMBER 10, 2008
MC100ES6226
2.5V/3.3V DIFFERENTIAL LVPECL 1:9 CLOCK DISTRIBUTION BUFFER AND CLOCK DRIVER
Figure 3. MC100ES6226 Output Disable/Enable Timing
Table 7. AC Characteristics (VCC = 3.3 V ± 5% and 2.5 V ± 5%, TJ = 0°C to +110°C)(1), (2)
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VPP
Differential Input Voltage(3) (peak-to-peak)
3. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew.
0.2
0.3
1.3
V
VCMR
Differential Input Crosspoint Voltage(4)
4. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC)
range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay,
device and part-to-part skew.
1.0
VCC – 0.3
V
VX,OUT
Differential Output Crosspoint Voltage
VCC – 1.45
VCC – 1.1
V
VO(P-P)
Differential Output Voltage (peak-to-peak)
fO < 300 MHz
fO < 1.5 GHz
fO < 2.7 GHz
0.45
0.3
TBD
0.72
0.55
0.37
0.95
V
fCLK
Input Frequency
0
3000(5)
5. The MC100ES6226 is fully operational up to 3.0 GHz and is characterized up to 2.7 GHz.
MHz
tPD
Propagation Delay CLK to Qx[]
475
500
800
ps
Differential
tsk(O)
Output-to-Output Skew
(within QA[2:0])
(within QB[2:0])
(within QC[2:0])
(within device)
11
12
4
25
20
60
ps
Differential
tsk(PP)
Output-to-Output Skew
(part-to-part)
325
ps
Differential
tJIT(CC)
Output Cycle-to-Cycle Jitter
RMS (1
σ)
single frequency configuration
÷1/÷2 frequency configuration
1
ps
FSEL0 = FSEL1
FSEL0
≠ FSEL1
DCO
Output Duty Cycle
Qx =
÷1, fO < 300 MHz
Qx =
÷1, fO > 300 MHz
Qx =
÷2, fO < 300 MHz
Qx =
÷2, fO > 300 MHz
48
45
49
47.5
50
52
55
51
52.5
%
DCfref = 50%
tr, tf
Output Rise/Fall Time
0.05
200
ns
20% to 80%
tPDL(6)
6. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high).
Output Disable Time
2.5
T + tPD
4.5
T + tPD
ns
T = CLK period
tPLD(7)
7. Propagation delay OE assertion to output enabled (active).
Output Enable Time
3
T + tPD
5
T + tPD
ns
T = CLK period
tPDL (OE to Qx)
50%
tPLD (OE to Qx)
Outputs Disabled
CLK
OE
Qx
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相關代理商/技術參數 |
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|---|---|
| MC100ES6226ACR2 | 功能描述:時鐘驅動器及分配 FSL 1-9 Diff LVPECL Clk Div Fanout Buff. RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100ES6226FA | 功能描述:時鐘緩沖器 Buffer RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MC100ES6254AC | 功能描述:時鐘驅動器及分配 FSL Differential LVP ECL 2x2 Clock Switch RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100ES6254ACR2 | 功能描述:時鐘驅動器及分配 FSL Differential LVP ECL 2x2 Clock Switch RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100ES6254FA | 功能描述:時鐘緩沖器 Buffer RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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