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參數(shù)資料
| 型號： | MC100ES6221AE |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | LEAD FREE, LQFP-52 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 311K |
| 代理商： | MC100ES6221AE |
MC100ES6221
Rev 5, 04/2005
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc., 2005. All rights reserved.
Low Voltage 1:20 Differential
ECL/PECL/HSTL Clock Fanout Buffer
The MC100ES6221 is a bipolar monolithic differential clock fanout buffer.
Designed for most demanding clock distribution systems, the MC100ES6221
supports various applications that require the distribution of precisely aligned
differential clock signals. Using SiGe technology and a fully differential
architecture, the device offers very low skew outputs and superior digital signal
characteristics. Target applications for this clock driver is high performance clock
distribution in computing, networking and telecommunication systems.
Features
1:20 differential clock fanout buffer
100 ps maximum device skew
SiGe technology
Supports DC to 2 GHz operation of clock or data signals
ECL/PECL compatible differential clock outputs
ECL/PECL/HSTL compatible differential clock inputs
Single 3.3 V, –3.3 V, 2.5 V or –2.5 V supply
Standard 52 lead LQFP package with exposed pad for enhanced thermal
characteristics
Supports industrial temperature range
Pin and function compatible to the MC100EP221
52-lead Pb-free Package Available
Functional Description
The MC100ES6221 is designed for low skew clock distribution systems and
supports clock frequencies up to 2 GHz. The device accepts two clock sources.
The CLK0 input can be driven by ECL or PECL compatible signals, the CLK1 input accepts HSTL compatible signals. The
selected input signal is distributed to 20 identical, differential ECL/PECL outputs. If VBB is connected to the CLK0 or CLK1 input
and bypassed to GND by a 10 nF capacitor, the MC100ES6221 can be driven by single-ended ECL/PECL signals utilizing the
VBB bias voltage output.
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even
if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts
being used on that side should be terminated.
The MC100ES6221 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the
MC100ES6221 supports positive (PECL) and negative (ECL) supplies. The MC100ES6221 is pin and function compatible to the
MC100EP221.
MC100ES6221
LOW VOLTAGE DUAL
1:20 DIFFERENTIAL ECL/PECL/HSTL
CLOCK FANOUT BUFFER
AE SUFFIX
52-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 1336A-01
TB SUFFIX
52-LEAD LQFP PACKAGE
EXPOSED PAD
CASE 1336A-01
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| MC100ES6222AER2 | 100E SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100ES6221AER2 | 功能描述:時鐘緩沖器 FSL 1-20 Diff LVPECL Fanout Buffer RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MC100ES6221TB | 功能描述:時鐘緩沖器 Buffer RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MC100ES6222AE | 功能描述:時鐘緩沖器 FSL 1-15 Diff LVPECL Clk Div Fanout Buff. RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MC100ES6222AER2 | 功能描述:時鐘驅(qū)動器及分配 FSL 1-15 Diff LVPECL Clk Div Fanout Buff. RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100ES6222TB | 功能描述:時鐘緩沖器 Buffer RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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