參數(shù)資料
型號: MC100ES6220TB
廠商: MOTOROLA INC
元件分類: 時鐘及定時
英文描述: 100E SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
封裝: EXPOSED PAD, PLASTIC, LQFP-52
文件頁數(shù): 6/7頁
文件大小: 127K
代理商: MC100ES6220TB
7
MC100ES6220
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
701
APPLICATIONS INFORMATION
Understanding the junction temperature range of the
MC100ES6220
To make the optimum use of high clock frequency and low
skew capabilities of the MC100ES6220, the MC100ES6220 is
specified, characterized and tested for the junction tempera-
ture range of TJ=0°C to +110°C. Because the exact thermal
performance depends on the PCB type, design, thermal man-
agement and natural or forced air convection, the junction tem-
perature provides an exact way to correlate the application
specific conditions to the published performance data of this
datasheet. The correlation of the junction temperature range to
the application ambient temperature range and vice versa can
be done by calculation:
TJ = TA + Rthja Ptot
Assuming a thermal resistance (junction to ambient) of
17
°C/W (2s2p board, 200 ft/min airflow, see Table 8 on page
702) and a typical power consumption of 1049 mW (all outputs
terminated 50 ohms to VTT, VCC=3.3V, frequency indepen-
dent), the junction temperature of the MC100ES6220 is
approximately TA + 18 °C, and the minimum ambient tempera-
ture in this example case calculates to -18
°C (the maximum
ambient temperature is 92
°C. See Table 7). Exceeding the
minimum junction temperature specification of the
MC100ES6220 does not have a significant impact on the de-
vice functionality. However, the continuous use the
MC100ES6220 at high ambient temperatures requires thermal
management to not exceed the specified maximum junction
temperature. Please see the application note AN1545 for a
power consumption calculation guideline.
Table 7. Ambient temperature ranges (Ptot = 1049mW)
Rthja (2s2p board)
TA, mina
TA, max
Natural convection
20
°C/W
–21
°C
89
°C
100 ft/min
18
°C/W
–19
°C
91
°C
200 ft/min
17
°C/W
–18
°C
92
°C
400 ft/min
16
°C/W
–17
°C
93
°C
800 ft/min
15
°C/W
–16
°C
94
°C
a. The MC100ES6220 device function is guaranteed from
TA=-40 °C to TJ=110 °C
Maintaining Lowest Device Skew
The MC100ES6220 guarantees low output-to-output bank
skew of 100 ps and a part-to-part skew of max. 200 ps. To
ensure low skew clock signals in the application, both outputs
of any differential output pair need to be terminated identically,
even if only one output is used. When fewer than all nine out-
put pairs are used, identical termination of all output pairs with-
in the output bank is recommended. This will reduce the device
power consumption while maintaining minimum output skew.
Power Supply Bypassing
The MC100ES6220 is a mixed analog/digital product. The
differential architecture of the MC100ES6220 supports low
noise signal operation at high frequencies. In order to maintain
its superior signal quality, all VCC pins should be bypassed by
high-frequency ceramic capacitors connected to GND. If the
spectral frequencies of the internally generated switching
noise on the supply pins cross the series resonant point of an
individual bypass capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the noise bandwidth.
Figure 5. VCC Power Supply Bypass
VCC
MC100ES6220
VCC
33...100 nF
0.1 nF
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