參數(shù)資料
型號(hào): MC100ES6111AC
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 100E SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: LEAD FREE, LQFP-32
文件頁(yè)數(shù): 9/12頁(yè)
文件大小: 307K
代理商: MC100ES6111AC
Advanced Clock Drivers Devices
6
Freescale Semiconductor
MC100ES6111
Table 7. AC Characteristics (ECL: VEE = –3.3 V ± 5% or VEE = –2.5 V ± 5%, VCC = GND) or
(HSTL/PECL: VCC = 3.3 V ± 5% or VCC = 2.5 V ± 5%, VEE = GND, TJ = 0°C to +110°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA (PECL or ECL differential signals)
VPP
Differential Input Voltage(2) (peak-to-peak)
2. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tpd and
device-to-device skew.
0.15
1.3
V
VCMR
Differential Input Crosspoint Voltage(3)
PECL
3. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the
VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device
propagation delay, device and part-to-part skew.
VEE + 1.0
VCC – 0.3
V
fCLK
Input Frequency(4)
4. The MC100ES6111 is fully operational up to 3.0 GHz and is characterized up to 2.7 GHz.
2.7
GHz
Differential
tPD
Propagation Delay CLKA or CLKB to Q0–9
280
400
530
ps
Differential
Clock Input Pair CLKB, CLKB (HSTL differential signals)
VDIF
Differential Input Voltage (peak-to-peak)(5)
5. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tPD and device-to-device
skew.
0.4
1.0
V
VX
Differential Input Crosspoint Voltage(6)
6. VX (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX (AC)
range and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF (AC) impacts the device propagation delay,
device and part-to-part skew.
VEE + 0.1
VEE + 0.68
VEE + 0.9
VEE + 2.1
V
fCLK
Input Frequency
2.7
GHz
Differential
tPD
Propagation Delay CLKB to Q0-9
280
400
530
ps
Differential
ECL Clock Outputs (Q0-9, Q0-9)
VO(P-P)
Differential Output Voltage (peak-to-peak)
fO < 300 MHz
fO < 1.5 GHz
fO < 2.7 GHz
0.45
0.3
0.18
0.72
0.55
0.37
0.95
V
tsk(O)
Output-to-Output Skew
35
ps
Differential
tsk(PP)
Output-to-Output Skew (part-to-part) fO < 1.5 GHz
fO > 1.5 GHz
150
250
ps
Differential
tJIT(CC)
Output Cycle-to-Cycle Jitter
RMS (1
σ)
1
ps
tsk(P)
Output Pulse Skew(7)
7. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |.
75
ps
tr, tf
Output Rise/Fall Time
0.05
0.3
ns
20% to 80%
Figure 3. MC100ES6111 AC Test Reference
Differential Pulse
Generator
Z = 50
RT = 50
ZO = 50
DUT
MC100ES6111
VTT = GND
RT = 50
ZO = 50
VTT = GND
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