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參數資料
| 型號： | MC100ES6056EGR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 1/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK MUX 2:1 3GHZ 20-SOIC |
| 標準包裝： | 1,000 |
| 系列： | 100ES |
| 類型： | 多路復用器 |
| 電路數： | 2 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | ECL，LVDS，PECL |
| 輸出： | ECL，LVDS，PECL |
| 頻率 - 最大： | 3GHz |
| 電源電壓： | ±2.375 V ~ 3.8 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 20-SOIC |
| 包裝： | 帶卷 (TR) |
DATASHEET
2.5V, 3.3V ECL/LVPECL/LVDS Dual
Differential 2:1 Multiplexer
MC100ES6056
NRND
MC100ES6056 REVISION 6 FEBRUARY 26, 2013
1
2013 Integrated Device Technology, Inc.
The MC100ES6056 is a dual, fully differential 2:1 multiplexer. The differential data path
makes the device ideal for multiplexing low skew clock or other skew sensitive signals.
Multiple VBB pins are provided.
The VBB pin, an internally generated voltage supply, is available to this device only. For
single-ended input conditions, the unused differential input is connected to VBB as a
switching reference voltage. VBB may also rebias AC coupled inputs. When used,
decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5
mA. When not used, VBB should be left open.
The device features both individual and common select inputs to address both data
path and random logic applications.
The 100ES Series contains temperature compensation.
Features
360 ps Typical Propagation Delays
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V
ECL Mode Operating Range: VCC = 0 V with VEE = –2.375 V to –3.8 V
Open Input Default State
Separate and Common Select
Q Output Will Default LOW with Inputs Open or at VEE
VBB Outputs
LVDS Input Compatible
20-Lead Pb-Free Package Available
ORDERING INFORMATION
Device
Package
MC100ES6056DT
TSSOP-20
MC100ES6056DTR2
TSSOP-20
MC100ES6056EJ
TSSOP-20 (Pb-Free)
MC100ES6056EJR2
TSSOP-20 (Pb-Free)
MC100ES6056EG
MC100ES6056EGR2
SOIC-20 (Pb-Free)
DT SUFFIX
20-LEAD TSSOP PACKAGE
CASE 948E-03
EJ SUFFIX
20-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948E-03
EG SUFFIX
20-LEAD SOIC PACKAGE
Pb-FREE PACKAGE
CASE 751D-07
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
4
3
5
6789
10
2
1
17
18
16
15
14
13
12
11
19
20
10
1
0
VCC
Q0
SEL0 COM_SEL SEL1 VCC
Q1
VEE
D0a
VBB0
D0b
D1a
VBB1
D1b
Figure 1. 20-Lead Pinout (Top View) and Logic Diagram
Product Discontinuance Notice – Last Time Buy Expires on (12/23/2013)
NRND – Not Recommend for New Designs
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