參數(shù)資料
型號: MC100ES6039EGR2
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/9頁
文件大小: 0K
描述: IC CLK GENERATION CHIP 20-SOIC
標(biāo)準(zhǔn)包裝: 1,000
類型: 時鐘發(fā)生器
PLL:
輸入: ECL,HSTL,LVDS,PECL
輸出: ECL,PECL
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.8 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC
包裝: 帶卷 (TR)
DATASHEET
3.3V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/6
Clock Generation Chip
MC100ES6039
MC100ES6039 REVISION 3 FEBRUARY 5, 2013
1
2013 Integrated Device Technology, Inc.
The MC100ES6039 is a low skew
2/4, 4/6 clock generation chip designed explicitly
for low skew clock generation applications. The internal dividers are synchronous to each
other, therefore, the common output edges are all precisely aligned. The device can be
driven by either a differential or single-ended ECL or, if positive power supplies are used,
LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC
coupled into the device.
The common enable (EN) is synchronous so that the internal dividers will only be
enabled/disabled when the internal clock is already in the LOW state. This avoids any
chance of generating a runt clock pulse on the internal clock when the device is enabled/
disabled as can happen with an asynchronous control. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore, all associated specification limits
are referenced to the negative edge of the clock input.
Upon startup, the internal flip-flops will attain a random state; therefore, for systems
which utilize multiple ES6039s, the master reset (MR) input must be asserted to ensure
synchronization. For systems which only use one ES6039, the MR pin need not be
exercised as the internal divider design ensures synchronization between the
2/4 and the
4/6 outputs of a single device. All VCC and VEE pins must be externally connected to
power supply to guarantee proper operation.
The 100ES Series contains temperature compensation.
Features
Maximum Frequency >1.0 GHz Typical
50 ps Output-to-Output Skew
PECL Mode Operating Range: VCC = 3.135 V to 3.8 V with VEE = 0 V
ECL Mode Operating Range: VCC = 0 V with VEE = –3.135 V to –3.8 V
Open Input Default State
Synchronous Enable/Disable
Master Reset for Synchronization of Multiple Chips
VBB Output
LVDS and HSTL Input Compatible
20-Lead Pb-Free Package Available
ORDERING INFORMATION
Device
Package
MC100ES6039DW
SO-20
MC100ES6039DWR2
SO-20
MC100ES6039EG
SO-20 (Pb-Free)
MC100ES6039EGR2
SO-20 (Pb-Free)
DW SUFFIX
20-LEAD SOIC PACKAGE
CASE 751D-07
EG SUFFIX
20-LEAD SOIC PACKAGE
Pb-FREE PACKAGE
CASE 751D-07
Product Discontinuance Notice – Last Time Buy Expires on (12/19/2013)
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