參數(shù)資料
型號: MC100EPT20MNR4G
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: 3.3V LVTTL/LVCMOS to Differential LVPECL Translator
中文描述: TTL/CMOS TO PECL TRANSLATOR, COMPLEMENTARY OUTPUT, DSO8
封裝: LEAD FREE, DFN-8
文件頁數(shù): 5/10頁
文件大?。?/td> 149K
代理商: MC100EPT20MNR4G
MC10EPT20, MC100EPT20
http://onsemi.com
5
Table 6. 100EPT PECL OUTPUT DC CHARACTERISTICS
V
CC
= 3.3 V, GND = 0 V (Note 4)
Symbol
Characteristic
40
°
C
25
°
C
85
°
C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
I
CC
Negative Power Supply Current
20
25
30
22
27
32
23
28
33
mA
V
OH
Output HIGH Voltage (Note 5)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
V
OL
Output LOW Voltage (Note 5)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Output parameters vary 1:1 with V
CC
.
5. All loading with 50 to V
CC
2.0 V.
Table 7. AC CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND = 0 V (Note 6)
Symbol
Characteristic
40
°
C
25
°
C
85
°
C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
f
max
Maximum Input Clock Frequency
> 1
> 1
> 1
GHz
t
PLH
,
t
PHL
Propagation Delay to
Output Differential
280
350
430
300
370
450
320
400
490
ps
t
SKEW
Device
to
Device Skew (Note 7)
150
150
170
ps
t
JITTER
RMS Random Clock Jitter
1
2
1
2
1
2
ps
t
r
t
f
Output Rise/Fall Times
(20%
80%)
Q, Q
70
100
170
80
120
180
90
140
190
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Measured using a LVTTL source, 50% duty cycle clock source. All loading with 50 to V
CC
2.0 V.
7. Skew is measured between outputs under identical transitions.
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