參數(shù)資料
型號(hào): MC100EP91DWR2
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: 2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator
中文描述: TRIPLE ECL TO PECL TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO20
封裝: SOP-20
文件頁數(shù): 6/10頁
文件大?。?/td> 174K
代理商: MC100EP91DWR2
MC100EP91
http://onsemi.com
6
Table 7. AC CHARACTERISTICS
V
CC
= 2.375 V to 3.8 V; V
EE
=
3.0 V to
5.5 V; GND = 0 V
Symbol
Characteristic
40
°
C
25
°
C
85
°
C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
V
OUTPP
Output Voltage Amplitude
(Figure 4)
(Note 9)
f
in
f
in
f
in
1.0 GHz
1.5 GHz
2.0 GHz
575
525
300
800
750
600
600
525
250
800
750
550
550
400
150
800
750
500
mV
t
PLH
t
PHL0
Propagation Delay
D to Q
Differential
Single
Ended
375
300
500
450
600
650
375
300
500
450
600
675
400
300
550
500
650
750
ps
t
SKEW
Pulse Skew (Note 10)
Output
to
Output (Note 11)
Part
to
Part (Diff)
(Note 11)
15
25
50
75
95
125
15
30
50
75
105
125
15
30
70
80
105
150
ps
t
JITTER
RMS Random Clock Jitter (Note 12)
Peak
to
Peak Data Dependant Jitter f
in
= 2.0 Gb/s
(Note 13)
f
in
= 2.0 GHz
0.5
20
2.0
0.5
20
2.0
0.5
20
2.0
ps
V
INPP
Input Voltage Swing (Differential Configuration)
(Note 14)
200
800
1200
200
800
1200
200
800
1200
mV
t
r
, t
f
Output Rise/Fall Times @ 50 MHz
(20%
80%)
Q, Q
75
150
250
75
150
250
75
150
275
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to GND
2.0 V. Input edge rates 150 ps (20%
80%).
10.Pulse Skew = |t
t
|
11.Skews are valid across specified voltage range, part
to
part skew is for a given temperature.
12.RMS Jitter with 50% Duty Cycle Input Clock Signal.
13.Peak
to
Peak Jitter with input NRZ PRBS 2
31
1
at 2.0 Gb/s.
14.Input voltage swing is a single
ended measurement operating in differential mode. The device has a DC gain of
50.
Figure 4. Output Voltage Amplitude (V
OUTPP
) / RMS Jitter vs.
Input Frequency (f
in
) at Ambient Temperature (Typical)
INPUT FREQUENCY (GHz)
0.5
1.0
1.5
2.0
2.5
250
350
450
550
650
750
850
O
(
R
9.0
8.0
10
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
RMS JITTER
AMP
Figure 5. AC Reference Measurement
D
D
Q
Q
t
PHL
t
PLH
V
INPP
= V
IH
(D)
V
IL
(D)
V
OUTPP
= V
OH
(Q)
V
OL
(Q)
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