參數(shù)資料
型號: MC100EP91DWG
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: 2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator
中文描述: TRIPLE ECL TO PECL TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO20
封裝: LEAD FREE, SOP-20
文件頁數(shù): 2/10頁
文件大?。?/td> 174K
代理商: MC100EP91DWG
MC100EP91
http://onsemi.com
2
D1
D1
D2
Q0
Q1
Q1
V
EE
D0
Q0
D2
D0
V
CC
V
BB
Figure 1. Logic Diagram
Q2
Q2
GND
Positive Level
Input
NECL Output
R1
R1
R1
R1
R1
R1
R2
R2
R2
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Default
State
Description
SOIC
QFN
1, 20
3, 4, 12
V
CC
Positive Supply Voltage. All V
CC
Pins must be Externally
Connected to Power Supply to Guarantee Proper Opera-
tion.
10
15, 16
V
EE
Negative Supply Voltage. All V
EE
Pins must be Externally
Connected to Power Supply to Guarantee Proper Opera-
tion.
14, 17
19, 20, 23,
24
GND
Ground.
4, 7
7, 11
V
BB
ECL Reference Voltage Output
2, 5, 8
5, 8, 13
D[0:2]
LVPECL, LVDS, LVTTL,
LVCMOS, CML, HSTL Input
Low
Noninverted Differential Inputs [0:2]. Internal 75 k to V
EE
.
3, 6, 9
6, 9, 14
D[0:2]
LVPECL, LVDS,
LVTTL,LVCMOS, CML,
HSTL Input
High
Inverted Differential Inputs [0:2]. Internal 75 k to V
EE
and
75 k to V
CC
. When Inputs are Left Open They Default to
(V
CC
V
EE
19,16,13
2, 18, 22
Q[0:2]
NECL Output
Noninverted Differential Outputs [0:2]. Typically Terminated
with 50 to V
TT
= V
CC
2 V
18,15,12
1, 21, 17
Q[0:2]
NECL Output
Inverted Differential Outputs [0:2]. Typically Terminated with
50 to V
TT
= V
CC
2 V
11
10
NC
No Connect. The NC Pin is NOT Electrically Connected to
the Die and may Safely be Connected to Any Voltage from
V
EE
to V
CC
.
N/A
EP
Exposed Pad. (Note 1)
1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat
sinking conduit.
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