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參數(shù)資料
型號: MC100EP16VSDR2G
廠商: ON Semiconductor
文件頁數(shù): 5/12頁
文件大?。?/td> 0K
描述: IC RCVR/DRVR 5V DIFF ECL 8-SOIC
標(biāo)準(zhǔn)包裝: 2,500
系列: 100EP
邏輯類型: 差分接收器/驅(qū)動器
電源電壓: 3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOICN
包裝: 帶卷 (TR)
MC100EP16VS
http://onsemi.com
2
1
2
3
45
6
7
8
Q
VEE
VCC
Figure 1. 8Lead Pinout (Top View) and Logic Diagram
D
Q
D
VBB
VCTRL
D*, D**
ECL Data Inputs
Q, Q
ECL Data Outputs
VCTRL*
Output Swing Control
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
NC
No Connect
Table 1. PIN DESCRIPTION
* Pins will default LOW when left open.
** Pins will default to VCC/2 when left open.
PIN
FUNCTION
2, 3
6, 7
1
4
8
5
(DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
to the most negative supply (GND)
or leave unconnected, floating open.
EP
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
37.5 kW
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
PbFree Pkg
SOIC8
TSSOP8
DFN8
Level 1
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V0 @ 0.125 in
Transistor Count
140 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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