參數(shù)資料
型號: MC100EP08MNR4
廠商: ON SEMICONDUCTOR
元件分類: 門電路
英文描述: 100E SERIES, 2-INPUT XOR/XNOR GATE, PDSO8
封裝: DFN-8
文件頁數(shù): 8/11頁
文件大?。?/td> 128K
代理商: MC100EP08MNR4
MC10EP08, MC100EP08
http://onsemi.com
6
Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 17)
-40
°C
25
°C
85
°C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
20
28
36
20
30
38
20
32
40
mA
VOH
Output HIGH Voltage (Note 18)
-1145
-1020
-895
-1145
-1020
-895
-1145
-1020
-895
mV
VOL
Output LOW Voltage (Note 18)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 19)
VEE + 2.0
0.0
VEE + 2.0
0.0
VEE + 2.0
0.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
D
0.5
-150
0.5
-150
0.5
-150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
17. Input and output parameters vary 1:1 with VCC.
18. All loading with 50
W to VCC - 2.0 V.
19. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 20)
-40
°C
25
°C
85
°C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fmax
Maximum Frequency (Figure 2)
> 3
GHz
tPLH,
tPHL
Propagation Delay to
Output Differential
D, D to Q, Q
170
220
280
180
250
300
200
270
320
ps
tJITTER
Cycle-to-Cycle Jitter (Figure 2)
0.2
< 1
0.2
< 1
0.2
< 1
ps
VPP
Input Voltage Swing
(Differential Configuration)
150
800
1200
150
800
1200
150
800
1200
mV
tr
tf
Output Rise/Fall Times
Q, Q
(20% - 80%)
70
120
170
80
130
180
100
150
200
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50
W to VCC - 2.0 V.
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