- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨�(m菐i)璩�(m脿i)IC缍�(w菐ng) > PDF鐩寗7986 > MC100EP01DTR2G (ON Semiconductor)IC GATE OR/NOR ECL 4INP 8-TSSOP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MC100EP01DTR2G |
| 寤犲晢锛� | ON Semiconductor |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 8/10闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC GATE OR/NOR ECL 4INP 8-TSSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 2,500 |
| 绯诲垪锛� | 100EP |
| 閭忚集椤�(l猫i)鍨嬶細 | 鎴栭潪闁€(m茅n)/鎴栭杸(m茅n) |
| 闆昏矾鏁�(sh霉)锛� | 1 |
| 杓稿叆鏁�(sh霉)锛� | 4 |
| 鏂藉瘑鐗硅Ц鐧�(f膩)鍣ㄨ几鍏ワ細 | 鐒�(w煤) |
| 杓稿嚭椤�(l猫i)鍨嬶細 | 宸垎 |
| 闆绘簮闆诲锛� | 3 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤�(l猫i)鍨嬶細 | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-TSSOP |
| 鍖呰锛� | 甯跺嵎 (TR) |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)鐣�(d膩ng)鍓嶇8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)
MC10EP01, MC100EP01
http://onsemi.com
7
ORDERING INFORMATION
Device
Package
Shipping
MC10EP01D
SOIC8
98 Units / Rail
MC10EP01DG
SOIC8
(PbFree)
98 Units / Rail
MC10EP01DR2
SOIC8
2500 / Tape & Reel
MC10EP01DR2G
SOIC8
(PbFree)
2500 / Tape & Reel
MC10EP01DT
TSSOP8
100 Units / Rail
MC10EP01DTG
TSSOP8
(PbFree)
100 Units / Rail
MC10EP01DTR2
TSSOP8
2500 / Tape & Reel
MC10EP01DTR2G
TSSOP8
(PbFree)
2500 / Tape & Reel
MC10EP01MNR4
DFN8
1000 / Tape & Reel
MC10EP01MNR4G
DFN8
(PbFree)
1000 / Tape & Reel
MC100EP01D
SOIC8
98 Units / Rail
MC100EP01DG
SOIC8
(PbFree)
98 Units / Rail
MC100EP01DR2
SOIC8
2500 / Tape & Reel
MC100EP01DR2G
SOIC8
(PbFree)
2500 / Tape & Reel
MC100EP01DT
TSSOP8
100 Units / Rail
MC100EP01DTG
TSSOP8
(PbFree)
100 Units / Rail
MC100EP01DTR2
TSSOP8
2500 / Tape & Reel
MC100EP01DTR2G
TSSOP8
(PbFree)
2500 / Tape & Reel
MC100EP01MNR4
DFN8
1000 / Tape & Reel
MC100EP01MNR4G
DFN8
(PbFree)
1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
ECL Clock Distribution Techniques
AN1406/D
Designing with PECL (ECL at +5.0 V)
AN1503/D
ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
Metastability and the ECLinPS Family
AN1568/D
Interfacing Between LVDS and ECL
AN1672/D
The ECL Translator Guide
AND8001/D Odd Number Counters Design
AND8002/D Marking and Date Codes
AND8020/D Termination of ECL Logic Devices
AND8066/D Interfacing with ECLinPS
AND8090/D AC Characteristics of ECL Devices
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| MC100EP01DR2G | IC GATE OR/NOR ECL 4INPUT 8-SOIC |
| MC100LVEL05DTR2G | IC GATE AND/NAND ECL 2INP 8TSSOP |
| TXR40AB45-1406AI | ADPTR TINEL LOCK ANG SHELL 15, D |
| MC10EP08DR2G | IC GATE XOR/XNOR ECL 2INP 8-SOIC |
| TXR54AB00-1805AI | ADPTR TINEL LOCK STR SHELL 18,27 |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MC100EP01MNR4 | 鍒堕€犲晢:ONSEMI 鍒堕€犲晢鍏ㄧū(ch膿ng):ON Semiconductor 鍔熻兘鎻忚堪:3.3V / 5V ECL 4−Input OR/NOR |
| MC100EP01MNR4G | 鍔熻兘鎻忚堪:閭忚集闁€(m茅n) BBG ECL OR/NOR 4INPT RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝�:OR 閭忚集绯诲垪:LVC 鏌垫サ鏁�(sh霉)閲�:2 绶氳矾鏁�(sh霉)閲忥紙杓稿叆/杓稿嚭锛�:2 / 1 楂橀浕骞宠几鍑洪浕娴�:- 16 mA 浣庨浕骞宠几鍑洪浕娴�:16 mA 鍌虫挱寤堕伈鏅�(sh铆)闁�:3.8 ns 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.65 V 鏈€澶у伐浣滄韩搴�:+ 125 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DCU-8 灏佽:Reel |
| MC100EP05 | 鍒堕€犲晢:ONSEMI 鍒堕€犲晢鍏ㄧū(ch膿ng):ON Semiconductor 鍔熻兘鎻忚堪:3.3V / 5VECL 2-Input Differential AND/NAND |
| MC100EP05D | 鍔熻兘鎻忚堪:閭忚集闁€(m茅n) 3.3V/5V ECL 2-Input RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝�:OR 閭忚集绯诲垪:LVC 鏌垫サ鏁�(sh霉)閲�:2 绶氳矾鏁�(sh霉)閲忥紙杓稿叆/杓稿嚭锛�:2 / 1 楂橀浕骞宠几鍑洪浕娴�:- 16 mA 浣庨浕骞宠几鍑洪浕娴�:16 mA 鍌虫挱寤堕伈鏅�(sh铆)闁�:3.8 ns 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.65 V 鏈€澶у伐浣滄韩搴�:+ 125 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DCU-8 灏佽:Reel |
| MC100EP05DG | 鍔熻兘鎻忚堪:閭忚集闁€(m茅n) 3.3V/5V ECL 2-Input Diff AND/NAND RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝�:OR 閭忚集绯诲垪:LVC 鏌垫サ鏁�(sh霉)閲�:2 绶氳矾鏁�(sh霉)閲忥紙杓稿叆/杓稿嚭锛�:2 / 1 楂橀浕骞宠几鍑洪浕娴�:- 16 mA 浣庨浕骞宠几鍑洪浕娴�:16 mA 鍌虫挱寤堕伈鏅�(sh铆)闁�:3.8 ns 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.65 V 鏈€澶у伐浣滄韩搴�:+ 125 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DCU-8 灏佽:Reel |
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