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參數(shù)資料
| 型號(hào)： | MC100E310FNR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:8 28-PLCC |
| 產(chǎn)品變化通告： | Dimensional change 21/Oct/2008 |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 系列： | 100E |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | ECL，PECL |
| 輸出： | ECL，PECL |
| 頻率 - 最大： | 900MHz |
| 電源電壓： | 4.2 V ~ 5.7 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
MC100E310
http://onsemi.com
5
40°C
25°C
85°C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fMAX
Maximum Toggle Frequency
700
900
700
900
700
900
MHz
tPLH
tPHL
Propagation Delay to Output
IN (differential) (Note 8)
IN (singleended) (Note 9)
525
500
725
750
550
750
800
575
600
775
850
ps
tskew
WithinDevice Skew (Note 10)
ParttoPart Skew (Diff)
75
250
50
200
50
200
ps
tJITTER
Random Clock Jitter (RMS)
< 1
ps
VPP
Input Voltage Swing
(Differential Configuration)
500
mV
tr/tf
Output Rise/Fall Time
(20%80%)
200
600
200
600
200
600
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. VEE can vary 0.46 V / +0.8 V.
8. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 112) of the ON Semiconductor
High Performance ECL Data Book (DL140/D).
9. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
10.The withindevice skew is defined as the worst case difference between any two similar delay paths within a single device.
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