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參數(shù)資料
| 型號： | MC-4R64FKE8S-845 |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | Direct Rambus DRAM SO-RIMM Module |
| 中文描述： | 32M X 18 DIRECT RAMBUS DRAM MODULE, DMA160 |
| 封裝： | SORIMM-160 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 151K |
| 代理商： | MC-4R64FKE8S-845 |
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Data Sheet E0140N31 (Ver. 3.1)
5
MC-4R64FKE8S
Module Connector Pad Description
(1/2)
Signal
I/O
Type
Description
GND
–
Ground reference for RDRAM core and interface.
LCFM
I
RSL
Clock from master.
Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
LCFMN
I
RSL
Clock from master.
Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
LCMD
I
VCMOS
Serial Command used to read from and write to the control registers. Also used
for power management.
LCOL4..LCOL0
I
RSL
Column bus.
5-bit bus containing control and address information for column
accesses.
LCTM
I
RSL
Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Positive polarity.
LCTMN
I
RSL
Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Negative polarity.
LDQA8..LDQA0
I/O
RSL
Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. LDQA8 is non-functional on modules with x16 RDRAM devices.
LDQB8..LDQB0
I/O
RSL
Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. LDQB8 is non-functional on modules with x16 RDRAM devices.
LROW2..LROW0
I
RSL
Row bus. 3-bit bus containing control and address information for row accesses.
LSCK
I
VCMOS
Serial clock input.
Clock source used to read from and write to the RDRAM
control registers.
NC
–
These pads are not connected. These 8 connector pads are reserved for future
use.
RCFM
I
RSL
Clock from master.
Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
RCFMN
I
RSL
Clock from master.
Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
RCMD
I
VCMOS
Serial Command Input used to read from and write to the control registers. Also
used for power management.
RCOL4..RCOL0
I
RSL
Column bus.
5-bit bus containing control and address information for column
accesses.
RCTM
I
RSL
Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Positive polarity.
RCTMN
I
RSL
Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Negative polarity.
RDQA8..RDQA0
I/O
RSL
Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. RDQA8 is non-functional on modules with x16 RDRAM devices.
RDQB8..RDQB0
I/O
RSL
Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. RDQB8 is non-functional on modules with x16 RDRAM devices.
RROW2..RROW0
I
RSL
Row bus. 3-bit bus containing control and address information for row accesses.
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| MC-4R96CEE6B | 制造商:NEC 制造商全稱:NEC 功能描述:Direct Rambus DRAM RIMM Module 96M-BYTE 48M-WORD x 16-BIT |
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