參數(shù)資料
型號(hào)： MC-4R64FKE6D
廠(chǎng)商： Elpida Memory, Inc.
英文描述： Direct Rambus DRAM RIMM Module 64M-BYTE (32M-WORD x 16-BIT)
中文描述： 直接Rambus的內(nèi)存模組RIMM的6400字節(jié)（32兆字x 16位）
文件頁(yè)數(shù)： 5/14頁(yè)
文件大小： 135K
代理商： MC-4R64FKE6D
Data Sheet E0092N20 (Ver. 2.0)
5
MC-4R64FKE6D
Module Connector Pad Description
(1/2)
Signal
I/O
Type
Description
GND
–
–
Ground reference for RDRAM core and interface. 72 PCB connector pads.
LCFM
I
RSL
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
LCFMN
I
RSL
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
LCMD
I
V
CMOS
Serial Command used to read from and write to the control registers. Also used
for power management.
LCOL4..LCOL0
I
RSL
Column bus. 5-bit bus containing control and address information for column
accesses.
LCTM
I
RSL
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
LCTMN
I
RSL
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
LDQA8..LDQA0
I/O
RSL
Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. LDQA8 is non-functional on modules with x16 RDRAM devices.
LDQB8..LDQB0
I/O
RSL
Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. LDQB8 is non-functional on modules with x16 RDRAM devices.
LROW2..LROW0
I
RSL
Row bus. 3-bit bus containing control and address information for row accesses.
LSCK
I
V
CMOS
Serial clock input. Clock source used to read from and write to the RDRAM
control registers.
NC
–
–
These pads are not connected. These 24 connector pads are reserved for future
use.
RCFM
I
RSL
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
RCFMN
I
RSL
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
RCMD
I
V
CMOS
Serial Command Input used to read from and write to the control registers. Also
used for power management.
RCOL4..RCOL0
I
RSL
Column bus. 5-bit bus containing control and address information for column
accesses.
RCTM
I
RSL
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
RCTMN
I
RSL
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
RDQA8..RDQA0
I/O
RSL
Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. RDQA8 is non-functional on modules with x16 RDRAM devices.
RDQB8..RDQB0
I/O
RSL
Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. RDQB8 is non-functional on modules with x16 RDRAM devices.
RROW2..RROW0
I
RSL
Row bus. 3-bit bus containing control and address information for row accesses.
相關(guān)PDF資料
PDF描述
MC-4R64FKE6D-653 Direct Rambus DRAM RIMM Module 64M-BYTE (32M-WORD x 16-BIT)
MC-4R64FKE6D-745 Direct Rambus DRAM RIMM Module 64M-BYTE (32M-WORD x 16-BIT)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC-4R64FKE6D-653 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:Direct Rambus DRAM RIMM Module 64M-BYTE (32M-WORD x 16-BIT)
MC-4R64FKE6D-745 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:Direct Rambus DRAM RIMM Module 64M-BYTE (32M-WORD x 16-BIT)
MC-4R64FKE6D-840 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:Direct Rambus DRAM RIMM Module 64M-BYTE (32M-WORD x 16-BIT)
MC-4R64FKE6D-845 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:Direct Rambus DRAM RIMM Module 64M-BYTE (32M-WORD x 16-BIT)
MC-4R64FKE8D 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:Direct Rambus DRAM RIMM Module 64M-BYTE (32M-WORD x 18-BIT)
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