參數(shù)資料
型號: MC-4R64FKE6D-840
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: Direct Rambus DRAM RIMM Module 64M-BYTE (32M-WORD x 16-BIT)
中文描述: 32M X 16 DIRECT RAMBUS DRAM MODULE, DMA184
封裝: SOCKET TYPE, RIMM-184
文件頁數(shù): 9/14頁
文件大?。?/td> 458K
代理商: MC-4R64FKE6D-840
Data Sheet E0271N10 (Ver 1.0)
9
MC-4R64FKE6D-840
AC Electrical Specifications
Symbol
Parameter and Conditions
MIN.
TYP.
MAX.
Unit
Z
Module Impedance of RSL signals
25.2
28.0
30.8
Module Impedance of SCK and CMD signals
23.8
28.0
32.2
T
PD
Average clock delay from finger to finger of all RSL clock nets
1.28
ns
(CTM, CTMN,CFM, and CFMN)
T
PD
Propagation delay variation of RSL signals with respect to TPD
Note1,2
21
+21
ps
T
PD-CMOS
Propagation delay variation of SCK signal with respect to an average clock
delay
Note1
250
+250
ps
T
PD- SCK,CMD
Propagation delay variation of CMD signal with respect to SCK signal
200
+200
ps
V
α
/V
IN
Attenuation Limit
12.0
%
V
XF
/V
IN
Forward crosstalk coefficient
(300ps input rise time 20% - 80%)
2.0
%
V
XB
/V
IN
Backward crosstalk coefficient
(300ps input rise time 20% - 80%)
1.5
%
R
DC
DC Resistance Limit
0.6
Notes 1.
T
PD
or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM,
CTMN, CFM, and CFMN).
2.
If the RIMM module meets the following specification, then it is compliant to the specification.
If the RIMM module does not meet these specifications, then the specification can be adjusted by the
“Adjusted
T
PD
Specification” table.
Adjusted
T
PD
Specification
Symbol
Parameter and conditions
Adjusted MIN./MAX.
Absolute
Unit
MIN.
MAX.
T
PD
Propagation delay variation of RSL signals with respect to T
PD
+/
[17+(18*N*
Z0)]
Note
30
+30
ps
Note
N = Number of RDRAM devices installed on the RIMM module.
Z0 = delta Z0% = (MAX. Z0
MIN. Z0) / (MIN. Z0)
(MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers
on the module.)
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