參數(shù)資料
型號(hào): MC-4R256FKK8K
廠商: Elpida Memory, Inc.
英文描述: 256MB 32-bit Direct Rambus DRAM RIMM Module
中文描述: 256MB的32位直接Rambus的內(nèi)存RIMM的模塊
文件頁(yè)數(shù): 4/13頁(yè)
文件大小: 91K
代理商: MC-4R256FKK8K
MC-4R256FKK8K
Preliminary Data Sheet E0253N10 (Ver. 1.0)
4
Module Connector Pad Description
Signal
Module
connector pads
I/O
Type
Description
Clock From Master. Connects to left RDRAM device on
"Thru" Channel. Interface clock used for receiving RSL
signals from the controller. Positive polarity.
Clock From Master. Connects to right RDRAM device on
"Thru" Channel. Interface clock used for receiving RSL
signals from the controller. Positive polarity.
Clock From Master. Connects to left RDRAM device on
"Thru" Channel. Interface clock used for receiving RSL
signals from the controller. Negative polarity.
Clock From Master. Connects to right RDRAM device on
"Thru" Channel. Interface clock used for receiving RSL
signals from the controller. Negative polarity.
Serial Command Input used to read from and write to the
control registers. Also used for power management.
Connects to left RDRAM device on "Thru" Channel.
Serial Command Input used to read from and write to the
control registers. Also used for power management.
Connects to right RDRAM device on "Thru" Channel.
"Thru" Channel Column bus. 5-bit bus containing control and
address information for column accesses. Connects to left
RDRAM device on "Thru" Channel.
"Thru" Channel Column bus. 5-bit bus containing control and
address information for column accesses. Connects to right
RDRAM device on "Thru" Channel.
Clock To Master. Connects to left RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to
the controller. Positive polarity.
Clock To Master. Connects to right RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to
the controller. Positive polarity.
Clock To Master. Connects to left RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to
the controller. Negative polarity.
Clock To Master. Connects to right RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to
the controller. Negative polarity.
"Thru" Channel Data bus A. A 9-bit bus carrying a byte of
read or write data between the controller and RDRAM devices
on “Thru” Channel. Connects to left RDRAM device on "Thru"
Channel. DQA8_THRU_L is non-functional on modules with
x16 RDRAM devices.
"Thru" Channel Data bus A. A 9-bit bus carrying a byte of
read or write data between the controller and RDRAM devices
on “Thru” Channel. Connects to right RDRAM device on
"Thru" Channel. DQA8_THRU_R is non-functional on
modules with x16 RDRAM devices.
"Thru" Channel Data bus B. A 9-bit bus carrying a byte of
read or write data between the controller and RDRAM devices
on “Thru” Channel. Connects to left RDRAM device on "Thru"
Channel. DQB8_THRU_L is non-functional on modules with
x16 RDRAM devices.
"Thru" Channel Data bus B. A 9-bit bus carrying a byte of
read or write data between the controller and RDRAM devices
on “Thru” Channel. Connects to right RDRAM device on
"Thru" Channel. DQB8_THRU_R is non-functional on
modules with x16 RDRAM devices.
Row bus. 3-bit bus containing control and address information
for row accesses. Connects to left RDRAM device on "Thru"
Channel.
CFM_THRU_L
A14
I
RSL
CFM_THRU_R
B54
I
RSL
CFMN_THRU_L
A16
I
RSL
CFMN_THRU_R
B52
I
RSL
CMD_THRU_L
B2
I
VCMOS
CMD_THRU_R
A73
I
VCMOS
COL4_THRU_L..
COL0_THRU_L
A20, B20, A22, B22,
A24
I
RSL
COL4_THRU_R..
COL0_THRU_R
B48, A48, B46, A46,
B44
I
RSL
CTM_THRU_L
B14
I
RSL
CTM_THRU_R
A54
I
RSL
CTMN_THRU_L
B12
I
RSL
CTMN_THRU_R
A56
I
RSL
DQA8_THRU_L..
DQA0_THRU_L
A4, B4, A6, B6, A8,
B8, A10, B10, A12
I/O
RSL
DQA8_THRU_R..
DQA0_THRU_R
B67, A67, B65, A65,
B63, A63, B58, A58,
B56
I/O
RSL
DQB8_THRU_L..
DQB0_THRU_L
B32, A32, B30, A30,
B28, A28, B26, A26,
B24
I/O
RSL
DQB8_THRU_R..
DQB0_THRU_R
A36, B36, A38, B38,
A40, B40, A42, B42,
A44
I/O
RSL
ROW2_THRU_L..
ROW0_THRU_L
B16, A18, B18
I
RSL
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