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參數(shù)資料
| 型號： | MC-4R128CEE6B-745 |
| 廠商： | NEC Corp. |
| 英文描述： | Direct Rambus DRAM RIMM Module 128M-BYTE 64M-WORD x 16-BIT |
| 中文描述： | 直接Rambus的128M的內(nèi)存RIMM的模塊技嘉6400字× 16位 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 129K |
| 代理商： | MC-4R128CEE6B-745 |
Preliminary Data Sheet M14539EJ1V1DS00
11
MC-4R128CEE6B, 4R128CEE6C
Timing Parameters
The following timing parameters are from the RDRAMs pins, not the RIMM. Please refer to the RDRAM data sheet
(
μ
PD488448, 488488) for detailed timing diagrams.
Para-
Description
MIN.
MAX.
Units
meter
-845
-745
-653
t
RC
Row Cycle time of RDRAM banks - the interval between ROWA packets with
ACT commands to the same bank.
28
28
28
—
t
CYCLE
t
RAS
RAS-asserted time of RDRAM bank - the interval between ROWA packet with ACT
command and next ROWR packet with PRER
Note 1
command to the same bank.
20
20
20
Note 2
64
μ
t
CYCLE
t
RP
Row Precharge time of RDRAM banks - the interval between ROWR packet with
PRER
bank.
Note 1
command and next ROWA packet with ACT command to the same
8
8
8
—
t
CYCLE
t
PP
Precharge-to-precharge time of RDRAM device - the interval between
successive ROWR packets with PRER
same device.
Note 1
commands to any banks of the
8
8
8
—
t
CYCLE
t
RR
RAS-to-RAS time of RDRAM device - the interval between successive ROWA
packets with ACT commands to any banks of the same device.
8
8
8
—
t
CYCLE
t
RCD
RAS-to-CAS Delay - the interval from ROWA packet with ACT command to
COLC packet with RD or WR command. Note - the RAS-to-CAS delay seen
by the RDRAM core (t
RCD-C
) is equal to t
RCD-C
=
1
+
t
RCD
because of differences
in the row and column paths through the RDRAM interface.
9
7
7
—
t
CYCLE
t
CAC
CAS Access delay - the interval from RD command to Q read data. The
equation for t
CAC
is given in the TPARM register.
8
8
8
12
t
CYCLE
t
CWD
CAS Write Delay - interval from WR command to D write data.
6
6
6
6
t
CYCLE
t
CC
CAS-to-CAS time of RDRAM bank - the interval between successive COLC
commands.
4
4
4
—
t
CYCLE
t
PACKET
Length of ROWA, ROWR, COLC, COLM or COLX packet.
4
4
4
4
t
CYCLE
t
RTR
Interval from COLC packet with WR command to COLC packet which causes
retire, and to COLM packet with bytemask.
8
8
8
—
t
CYCLE
t
OFFP
The interval (offset) from COLC packet with RDA command, or from COLC
packet with retire command (after WRA automatic precharge), or from COLC
packet with PREC command, or from COLX packet with PREX command to
the equivalent ROWR packet with PRER. The equation for t
OFFP
is given in the
TPARM register.
4
4
4
4
t
CYCLE
t
RDP
Interval from last COLC packet with RD command to ROWR packet with
PRER.
4
4
4
—
t
CYCLE
t
RTP
Interval from last COLC packet with automatic retire command to ROWR
packet with PRER.
4
4
4
—
t
CYCLE
Notes 1.
Or equivalent PREC or PREX command.
2.
This is a constraint imposed by the core, and is therefore in units of ms rather than t
CYCLE
.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MC-4R128CEE6B-845 | 制造商:NEC 制造商全稱:NEC 功能描述:Direct Rambus DRAM RIMM Module 128M-BYTE 64M-WORD x 16-BIT |
| MC-4R128CEE6C | 制造商:NEC 制造商全稱:NEC 功能描述:Direct Rambus DRAM RIMM Module 128M-BYTE 64M-WORD x 16-BIT |
| MC-4R128CEE6C-653 | 制造商:NEC 制造商全稱:NEC 功能描述:Direct Rambus DRAM RIMM Module 128M-BYTE 64M-WORD x 16-BIT |
| MC-4R128CEE6C-745 | 制造商:NEC 制造商全稱:NEC 功能描述:Direct Rambus DRAM RIMM Module 128M-BYTE 64M-WORD x 16-BIT |
| MC-4R128CEE6C-845 | 制造商:NEC 制造商全稱:NEC 功能描述:Direct Rambus DRAM RIMM Module 128M-BYTE 64M-WORD x 16-BIT |
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