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參數(shù)資料
| 型號： | MC-45D32CC721 |
| 廠商： | NEC Corp. |
| 英文描述： | 32 M-WORD BY 72-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE |
| 中文描述： | 32的M - Word的72位DDR同步動態(tài)RAM模塊無緩沖型 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 259K |
| 代理商： | MC-45D32CC721 |
Preliminary Data Sheet M14900EJ1V0DS00
6
MC-45D32CC721
DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
/CAS
latency
Grade
MIN.
MAX.
Unit
Notes
-C75
TBD
mA
Operating current
(ACT-PRE)
I
DD0
t
RC
= t
RC(MIN.)
, t
CK
= t
CK (MIN.)
, One bank,
Active-precharge, DQ, DM and DQS
inputs changing twice per clock cycle,
Address and control inputs changing
once per clock cycle
-C80
TBD
CL = 2
-C75
TBD
mA
1
-C80
TBD
CL = 2.5 -C75
TBD
Operating current
(ACT-READ-PRE)
I
DD1
t
RC
= t
RC(MIN.)
, t
CK
= t
CK (MIN.)
, One
bank, Active-read-precharge,
I
O
= 0 mA, Burst length = 2,
Address and control inputs
changing once per clock cycle
-C80
TBD
Precharge power down
standby current
I
DD2P
CKE
≤
V
IL(MAX.)
, t
CK
= t
CK(MIN.)
,
All banks idle, Power down mode
TBD
mA
Idle standby current
I
DD2N
CKE
≥
V
IH(MIN.)
, t
CK
= t
CK(MIN.)
, /CS
≥
V
IH(MIN.)
,
All banks idle, Address and other control inputs
changing once per clock cycle
CKE
≤
V
IL(MAX.)
, t
CK
= t
CK(MIN.)
, One bank active,
Power down mode
TBD
mA
Active power down
standby current
I
DD3P
TBD
mA
Active standby current
I
DD3N
/CS
≥
V
IH(MIN.)
, CKE
≥
V
IH(MIN.)
, t
CK
= t
CK(MIN.)
, t
RC
=
t
RAS(MAX.)
, One bank, Active-precharge, DQ, DM
and DQS inputs changing twice per clock
cycle, Address and other control inputs
changing once per clock cycle
TBD
mA
CL = 2
-C75
TBD
mA
2
-C80
TBD
CL = 2.5 -C75
TBD
Operating current
(Burst read)
I
DD4R
t
CK
= t
CK(MIN.)
, Continuous burst
read, Burst length = 2, I
O
=
0mA, One bank active,
Address and control inputs
changing once per clock cycle
-C80
TBD
CL = 2
-C75
TBD
mA
2
-C80
TBD
CL = 2.5 -C75
TBD
Operating current
(Burst write)
I
DD4W
t
CK
= t
CK(MIN.)
, Continuous burst
write, Burst length = 2, One
bank active, Address and
control inputs changing once
per clock cycle
-C80
TBD
CBR (auto) refresh current
I
DD5
t
RFC
= t
RFC(MIN.)
-C75
TBD
mA
-C80
TBD
Self refresh current
I
DD6
CKE
≤
0.2 V
TBD
mA
Notes 1.
I
DD1
depends on output loading and cycle rates. Specified values are obtained with the output open.
2.
I
DD4R
and I
DD4W
depend on output loading and cycle rates. Specified values are obtained with the output
open.
DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
MIN.
MAX.
Unit Notes
Input leakage current
I
I(L)
V
I
= 0 to 3.6 V, all other pins not under test = 0 V
TBD
TBD
μ
A
Output leakage current
I
O(L)
D
OUT
is disabled, V
O
= 0 to V
DD
Q + 0.3 V
TBD
TBD
μ
A
Output high current
I
OH
V
OUT
= V
DD
Q
0.43 V
TBD
mA
Output low current
I
OL
V
OUT
= 0.35 V
TBD
mA
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|---|---|
| MC-45D32CC721KFA-C75 | 制造商:NEC 制造商全稱:NEC 功能描述:32 M-WORD BY 72-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE |
| MC-45D32CC721KFA-C80 | 制造商:NEC 制造商全稱:NEC 功能描述:32 M-WORD BY 72-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE |
| MC-45D32CD641 | 制造商:NEC 制造商全稱:NEC 功能描述:32 M-WORD BY 64-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE |
| MC-45D32CD641KFA-C75 | 制造商:NEC 制造商全稱:NEC 功能描述:32 M-WORD BY 64-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE |
| MC-45D32CD641KFA-C80 | 制造商:NEC 制造商全稱:NEC 功能描述:32 M-WORD BY 64-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE |
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