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參數(shù)資料
| 型號(hào)： | MC-4564EC726PFB-A80 |
| 廠商： | NEC Corp. |
| 英文描述： | 64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE |
| 中文描述： | 64的M - Word的72位同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器模塊注冊(cè)的類型 |
| 文件頁(yè)數(shù)： | 1/16頁(yè) |
| 文件大小： | 292K |
| 代理商： | MC-4564EC726PFB-A80 |
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confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
1999
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4564EC726
64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
REGISTERED TYPE
Document No. M14460EJ2V0DS00 (2nd edition)
Date Published February 2000 NS CP(K)
Printed in Japan
The mark
#
shows major revised points.
Description
The MC-4564EC726 is a 67,108,864 words by 72 bits synchronous dynamic RAM module on which 36 pieces of
128 M SDRAM:
μ
PD45128441 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
67,108,864 words by 72 bits organization (ECC type)
Clock frequency and access time from CLK
Part number
/CAS latency
Clock frequency
Access time from CLK
Module type
(MAX.)
(MAX.)
MC-4564EC726EFB-A80
CL = 3
125
MHz
6
ns
PC100 Registered DIMM
CL = 2
100 MHz
6 ns
Rev. 1.2 Compliant
MC-4564EC726EFB-A10
CL = 3
100 MHz
6 ns
CL = 2
77 MHz
7 ns
MC-4564EC726PFB-A80
CL = 3
125
MHz
6
ns
CL = 2
100 MHz
6 ns
MC-4564EC726PFB-A10
CL = 3
100 MHz
6 ns
CL = 2
77 MHz
7 ns
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0 and BA1 (Bank Select)
Programmable burst-length (1, 2, 4, 8 and Full Page)
Programmable wrap sequence (Sequential
/
Interleave)
Programmable /CAS latency (2, 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
All DQs have 10
±
10
% of series resistor
Single 3.3
V
±
0.3
V power supply
LVTTL compatible
4,096 refresh cycles / 64
ms
Burst termination by Burst Stop command and Precharge command
168-pin dual in-line memory module (Pin pitch = 1.27
mm)
Registered type
Serial PD
Stacked monolithic technology
#
#
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