參數(shù)資料
型號: MC-4532DC726
廠商: NEC Corp.
英文描述: 32M-Word By72-BIT Dynamic RAM Module(32M×72位動態(tài)RAM模塊)
中文描述: 32M的詞By72位動態(tài)內(nèi)存模塊(32M的× 72位動態(tài)內(nèi)存模塊)
文件頁數(shù): 1/20頁
文件大?。?/td> 174K
代理商: MC-4532DC726
The information in this document is subject to change without notice.
1998
MOS INTEGRATED CIRCUIT
MC-4532DC726
32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
REGISTERED TYPE
DATA SHEET
Document No. M13201EJ6V0DS00 (6th edition)
Date Published October 1998 NS CP(K)
Printed in Japan
The mark
shows major revised points.
Description
The MC-4532DC726 is a 33,554,432 words by 72 bits synchronous dynamic RAM module on which 36 pieces of
64 M SDRAM :
μ
PD4564441 (Rev. E) are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
33,554,432 words by 72 bits organization (ECC type)
Clock frequency and Clock access time
Family
/CAS latency
Clock frequency
Clock access time
Power consumption (MAX.)
(MAX.)
(MAX.)
Active
Standby
MC-4532DC726-A80
CL = 3
125
MHz
6
ns
12.3 W
100.8 mW
CL = 2
100
MHz
6
ns
12.0 W
(CMOS level input )
MC-4532DC726-A10
CL = 3
100 MHz
6
ns
12.3
W
CL = 2
77 MHz
7
ns
12.0
W
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0 and BA1 (Bank Select)
Programmable burst-length (1, 2, 4, 8 and Full Page)
Programmable wrap sequence (Sequential
/
Interleave)
Programmable /CAS latency (2, 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
Single 3.3
V
±
0.3
V power supply
LVTTL compatible
4,096 refresh cycles/64
ms
Burst termination by Burst Stop command and Precharge command
All DQs have 10
±
10
% of series resistor
168-pin dual in-line memory module (Pin pitch = 1.27
mm)
Registered type
Serial PD
Stacked Module
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