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參數(shù)資料
| 型號： | MC-4532DA726PFB-A80 |
| 廠商： | NEC Corp. |
| 英文描述： | 32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE |
| 中文描述： | 32的M - Word的72位同步動態(tài)隨機存儲器模塊注冊的類型 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 153K |
| 代理商： | MC-4532DA726PFB-A80 |
6
MC-4532CC726
Data Sheet M13680EJ5V0DS00
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
Grade
MIN.
MAX.
Unit
Notes
Operating current
I
CC1
Burst length
=
1
/CAS latency = 2
-A80
1,170
mA
1
t
RC
≥
t
RC(MIN.)
, I
O
= 0
mA
-A10
1,170
/CAS latency = 3
-A80
1,170
-A10
1,170
Precharge standby current in
I
CC2
P
CKE
≤
V
IL(MAX.)
, t
CK
=
15
ns
18
mA
power down mode
I
CC2
PS CKE
≤
V
IL(MAX.)
, t
CK
=
∞
18
Precharge standby current in
non power down mode
I
CC2
N
CKE
≥
V
IH(MIN.)
, t
CK
=
15
ns, /CS
≥
V
IH(MIN.)
,
Input signals are changed one time during 30
ns.
360
mA
I
CC2
NS CKE
≥
V
IH(MIN.)
, t
CK
=
∞
Input signals are stable.
108
Active standby current in
I
CC3
P
CKE
≤
V
IL(MAX.)
, t
CK
=
15
ns
90
mA
power down mode
I
CC3
PS CKE
≤
V
IL(MAX.)
, t
CK
=
∞
72
Active standby current in
I
CC3
N
CKE
≥
V
IH(MIN.)
, t
CK
=
15
ns, /CS
≥
V
IH(MIN.)
,
Input signals are changed one time during 30
ns.
450
mA
non power down mode
I
CC3
NS CKE
≥
V
IH(MIN.)
, t
CK
=
∞
, Input signals are stable.
360
Operating current
I
CC4
t
CK
≥
t
CK(MIN.)
/CAS latency = 2
-A80
1,350
mA
2
(Burst mode)
I
O
= 0
mA
-A10
1,125
/CAS latency = 3
-A80
1,575
-A10
1,395
CBR (Auto) refresh current
I
CC5
t
RC
≥
t
RC(MIN.)
/CAS latency = 2
-A80
2,340
mA
3
-A10
2,340
/CAS latency = 3
-A80
2,340
-A10
2,340
Self refresh current
I
CC6
CKE
≤
0.2
V
36
mA
Input leakage current
I
I(L)
V
I
=
0 to 3.6
V,
All other pins not under test =
0 V
–
18
+
18
μ
A
Input leakage current (CKE1)
–500
+500
μ
A
Output leakage current
I
O(L)
D
OUT
is disabled, V
O
=
0 to 3.6
V
–
3
+
3
μ
A
High level output voltage
V
OH
I
O
=
–
4.0
mA
2.4
V
Low level output voltage
V
OL
I
O
=
+
4.0
mA
0.4
V
Notes 1.
I
CC1
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC1
is measured on condition that addresses are changed only one time during t
CK (MIN.)
.
2
. I
CC4
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC4
is measured on condition that addresses are changed only one time during t
CK (MIN.)
.
3.
I
CC5
is measured on condition that addresses are changed only one time during t
CK (MIN.)
.
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