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參數資料
| 型號： | MBM29SL160TD-12PFTR |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | 122 x 32 pixel format, LED Backlight available |
| 中文描述： | 2M X 8 FLASH 1.8V PROM, 120 ns, PDSO48 |
| 封裝： | PLASTIC, REVERSE, TSOP1-48 |
| 文件頁數： | 1/61頁 |
| 文件大?。?/td> | 715K |
| 代理商： | MBM29SL160TD-12PFTR |
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DS05-20877-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
16M (2M
×
8/1M
×
16) BIT
MBM29SL160TD
-10/-12
/MBM29SL160BD
-10/-12
I
FEATURES
Single 1.8 V read, program, and erase
Minimizes system level power requirements
Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
48-ball FBGA (Package suffix: PBT)
Minimum 100,000 program/erase cycles
High performance
100 ns maximum access time
Sector erase architecture
Eight 4K word and thirty one 32K word sectors in word mode
Eight 8K byte and thirty one 64K byte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
Boot Code Sector Architecture
T = Top sector
B = Bottom sector
One Time Protect (OTP) region
256 Byte of OTP accessible through a new “OTP Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
WP/ACC input pin
At V
IL
, allows protection of boot sectors, regardless of sector protection/unprotection status
At V
IH
, allows removal of boot sector protection
At V
HH
, increases program performance
Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
(Continued)
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
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