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參數(shù)資料
| 型號： | MBM29F004TC-70 |
| 廠商： | Spansion Inc. |
| 英文描述： | FLASH MEMORY CMOS 4 M (512 K X 8) BIT |
| 中文描述： | 閃存的CMOS 4米（512 kX的8）位 |
| 文件頁數(shù)： | 15/53頁 |
| 文件大?。?/td> | 288K |
| 代理商： | MBM29F004TC-70 |
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MBM29F004TC/004BC
-70/90
15
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Reset/Read mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
Figure 16 illustrates the Embedded Programming
TM
Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ
7
is “1” (See Write Operation Status section) at which time the device returns to read the
mode.
Figure 17 illustrates the Embedded Erase
TM
Algorithm using typical command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of CE or WE (whichever
happens first) , while the command (Data
=
30h) is latched on the rising edge of CE or WE (whichever happens
first) . After time-out of 50
μ
s from the rising edge of the last sector erase command, the sector erase operation
will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. This
sequence is followed with writes of the Sector Erase command (30h) to addresses in other sectors desired to
be concurrently erased. The time between writes must be less than 50
μ
s otherwise that command will not be
accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to
guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A
time-out of 50
μ
s from the rising edge of the last CE or WE will initiate the execution of the Sector Erase command
(s) . If another falling edge of the CE or WE occurs within the 50
μ
s time-out window the timer is reset. (Monitor
DQ
3
to determine if the sector erase timer window is still open, Write Operation Status section for DQ
3
, Sector
Erase Timer operation.) Resetting the device once execution has begun will corrupt the data in the sector. In
that case, restart the erase on those sectors and allow them to complete. Loading the sector erase buffer may
be done in any sequence and with any number of sectors (0 to 6) .
Sector erase does not require the user to program the device prior to erase. The device automatically programs
all memory locations in the sector (s) to be erased prior to electrical erase. When erasing a sector or sectors
the remaining unselected sectors are not affected. The system is not required to provide any controls or timings
during these operations.
The automatic sector erase begins after the 50
μ
s time out from the rising edge of the CE or WE pulse for the
last sector erase command pulse and terminates when the data on DQ
7
is “1” (See Write Operation Status
section) at which time the device returns to the read mode. Data polling must be performed at an address within
any of the sectors being erased.
Figure 17 illustrates the Embedded Erase
TM
Algorithm using typical command strings and bus operations.
Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable only during a Sector Erase operation
which includes the time-out period for sector erase and will be ignored during Chip Erase or Programming
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PDF描述 |
|---|---|
| MBM29F004TC-70PD | FLASH MEMORY CMOS 4 M (512 K X 8) BIT |
| MBM29F004TC-70PFTN | FLASH MEMORY CMOS 4 M (512 K X 8) BIT |
| MBM29F004TC-70PFTR | FLASH MEMORY CMOS 4 M (512 K X 8) BIT |
| MBM29F004TC-90PD | FLASH MEMORY CMOS 4 M (512 K X 8) BIT |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29F004TC-70PD | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 4 M (512 K X 8) BIT |
| MBM29F004TC-70PFTN | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 4 M (512 K X 8) BIT |
| MBM29F004TC-70PFTR | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 4 M (512 K X 8) BIT |
| MBM29F004TC-90PD | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 4 M (512 K X 8) BIT |
| MBM29F004TC-90PFTN | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 4 M (512 K X 8) BIT |
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