
72
FUJITSU SEMICONDUCTOR CONFIDENTIAL
r2.1
MB9A110 Series
DS706-00011-1v0-E
Separate Bus Access Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Min
Max
Unit
Vcc ≥ 4.5V
MOEX
Min pulse width
tOEW
MOEX
Vcc < 4.5V
MCLK×n-3
-
ns
Vcc ≥ 4.5V
-9
9
MCSX ↓ → Address
output delay time
tCSL – AV
MCSX[7:0]
MAD[24:0]
Vcc < 4.5V
-12
12
ns
Vcc ≥ 4.5V
MCLK×m+9
MOEX ↑ →
Address hold time
tOEH - AX
MOEX
MAD[24:0]
Vcc < 4.5V
0
MCLK×m+12
ns
Vcc ≥ 4.5V
MCLK×m-9 MCLK×m+9
MCSX ↓ →
MOEX ↓ delay time
tCSL - OEL
Vcc < 4.5V
MCLK×m-12 MCLK×m+12
ns
Vcc ≥ 4.5V
MCLK×m+9
MOEX ↑ →
MCSX ↑ time
tOEH - OSH
MOEX
MCSX[7:0]
Vcc < 4.5V
0
MCLK×m+12
ns
Vcc ≥ 4.5V
MCLK×m-9 MCLK×m+9
MCSX ↓ →
MDQM ↓ delay time
tCSL - RDQML
MOEX
MDQM[1:0]
Vcc < 4.5V
MCLK×m-12 MCLK×m+12
ns
Vcc ≥ 4.5V
20
-
Data set up →
MOEX ↑ time
tDS - OE
MOEX
MADATA[15:0]
Vcc < 4.5V
38
-
ns
Vcc ≥ 4.5V
MOEX ↑ →
Data hold time
tDH - OE
MOEX
MADATA[15:0]
Vcc < 4.5V
0
-
ns
Vcc ≥ 4.5V
MWEX
Min pulse width
tWEW
MWEX
Vcc < 4.5V
MCLK×n-3
-
ns
Vcc ≥ 4.5V
MCLK×m+9
MWEX ↑ → Address
output delay time
tWEH - AX
MWEX
MAD[24:0]
Vcc < 4.5V
0
MCLK×m+12
ns
Vcc ≥ 4.5V
MCLK×n-9
MCLK×n+9
MCSX ↓ →
MWEX ↓ delay time
tCSL - WEL
Vcc < 4.5V
MCLK×n-12 MCLK×n+12
ns
Vcc ≥ 4.5V
MCLK×m+9
MWEX ↑→
MCSX ↑ delay time
tWEH - CSH
MWEX
MCSX[7:0]
Vcc < 4.5V
0
MCLK×m+12
ns
Vcc ≥ 4.5V
MCLK×n-9
MCLK×n+9
MCSX ↓ →
MDQM ↓ delay time
tCSL-WDQML
MCSX
MDQM[1:0]
Vcc < 4.5V
MCLK×n-12 MCLK×n+12
ns
Vcc ≥ 4.5V
- 9
9
MWEX ↓ →
Data output time
tWEL - DV
Vcc < 4.5V
-12
12
ns
Vcc ≥ 4.5V
MCLK×m+9
MWEX ↑ →
Data hold time
tWEH - DX
MWEX
MADATA[15:0]
Vcc < 4.5V
0
MCLK×m+12
ns
Note: When the external load capacitance = 30pF (m = 0 to 15, n = 1 to 16).