參數(shù)資料
型號： MB9AF105NABGL
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PBGA112
封裝： 10 X 10 MM, 1.45 MM HEIGHT, 0.80 MM PITCH, PLASTIC, FBGA-112
文件頁數(shù)： 70/100頁
文件大?。?/td> 1055K
代理商： MB9AF105NABGL
71
FUJITSU SEMICONDUCTOR CONFIDENTIAL
r3.0
MB9A100A Series
(9) UART Timing
·
Synchronous serial (SPI = 0, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40
°C to + 85°C)
Vcc
< 4.5V
Vcc ≥ 4.5V
Parameter
Symbol
Pin
name
Conditions
Min
Max
Min
Max
Unit
Serial clock cycle time
tSCYC SCKx
4tcycp
-
4tcycp
-
ns
SCK
↓ → SOT delay time
tSLOVI
SCKx
SOTx
-30
+30
- 20
+ 20
ns
SIN
→ SCK ↑ setup time
tIVSHI
SCKx
SINx
50
-
30
-
ns
SCK
↑ → SIN hold time
tSHIXI
SCKx
SINx
Internal shift
clock
operation
0
-
0
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
2tcycp -
10
-
2tcycp -
10
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tcycp +
10
-
tcycp +
10
-
ns
SCK
↓ → SOT delay time
tSLOVE
SCKx
SOTx
-
50
-
30
ns
SIN
→ SCK ↑ setup time
tIVSHE
SCKx
SINx
10
-
10
-
ns
SCK
↑ → SIN hold time
tSHIXE
SCKx
SINx
20
-
20
-
ns
SCK fall time
tF
SCKx
-
5
-
5
ns
SCK rise time
tR
SCKx
External shift
clock
operation
-
5
-
5
ns
Notes:
·
The above characteristics apply to CLK synchronous mode.
·
tCYCP indicates the APB bus clock cycle time. Please see the block diagram to refer the APB bus
number which UART is connected.
·
These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
·
When the external load capacitance = 50pF.
DS706-00022-1v0-E
相關(guān)PDF資料
PDF描述
MB9AF105NAPF 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP100
MB9AF104NAPF 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP100
MB9AF104NAPMC 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP100
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