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參數(shù)資料
| 型號： | MB95R203P-G-SH-NE2 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 10 MHz, MICROCONTROLLER, PDIP24 |
| 封裝： | 6.40 MM X 22.86 MM, 4.80 MM HEIGHT, 1.778 MM PITCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 21/56頁 |
| 文件大?。?/td> | 1925K |
| 代理商： | MB95R203P-G-SH-NE2 |
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MB95R203
28
DS07-12625-3E
(2) Source Clock/Machine Clock
(Vcc
= 3.3 V, Vss = 0.0 V, TA = 20 °C to +70 °C)
(Continued)
Parameter
Symbol
Pin
name
Value
Unit
Remarks
Min
Typ
Max
Source clock
cycle time*1
(Clock before
division)
tSCLK
100
2000
ns
When using main external clock
Min : FCH
= 20 MHz, divided by 2
Max : FCH
= 1 MHz, divided by 2
1
μs
When using main CR oscillation clock
FCRH
= 1 MHz
61
μs
When using sub oscillation clock
FCL
= 32.768 kHz, divided by 2
20
μs
When using sub oscillation clock
FCRL
= 100 kHz, divided by 2
Source clock
frequency
FSP
0.5
10
MHz When using main oscillation clock
1
MHz When using main CR oscillation clock
FSPL
16.384
kHz When using sub oscillation clock
50
kHz When using sub CR clock
Machine clock
cycle time*2
(Minimum
instruction
execution time)
tMCLK
100
32000
ns
When using main oscillation clock
Min : FSP
= 10 MHz, no division
Max : FSP
= 0.5 MHz, divided by 16
1
16
μs
When using main CR clock
Min : FSP
= 1 MHz, no division
Max : FSP
= 1 MHz, divided by 16
61
976.5
μs
When using sub oscillation clock
Min : FSPL
= 16.384 kHz, no division
Max : FSPL
= 16.384 kHz, divided by 16
20
320
μs
When using sub CR clock
Min : FSPL
= 50 kHz, no division
Max : FSPL
= 50 kHz, divided by 16
Machine clock
frequency
FMP
0.031
10
MHz When using main oscillation clock
0.0625
1
MHz When using main CR clock
FMPL
1.024
16.384
kHz When using sub oscillation clock
3.125
50
kHz When using sub CR clock
FRAM clock
cycle time*3
(Minimum
instruction
execution time)
tFCLK
300
96000
ns
When using main oscillation clock
Min : FSP
= 10 MHz, divided by 3
Max : FSP
= 0.5 MHz, divided by 48
3
48
μs
When using main CR clock
Min : FSP=1 MHz, divided by 3
Max : FSP=1 MHz, divided by 48
183
2929.7
μs
When using sub oscillation clock
Min : FSPL
= 16.384 kHz, divided by 3
Max : FSPL
= 16.384 kHz, divided by 48
60
960
μs
When using sub CR clock
Min : FSPL
= 50 kHz, divided by 3
Max : FSPL
= 50 kHz, divided by 48
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