參數(shù)資料
型號: MB95F418KPMC-G-SNE2
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù): 60/76頁
文件大?。?/td> 3707K
代理商: MB95F418KPMC-G-SNE2
MB95410H/470H Series
DS702-00004-0v01-E
63
(VCC = 5.0 V
± 10%, AVSS = VSS = 0.0 V, TA = 40° C to +85° C)
(Continued)
Parameter Symbol
Pin
name
Conditions
Value*2
Unit
Remarks
Min
Max
SCL clock
“L” width
tLOW
SCL
R = 1.7 k
Ω,
C = 50 pF*1
(2
+ nm / 2) tMCLK 20
ns Master mode
SCL clock
“H” width
tHIGH
SCL
(nm / 2)tMCLK
20
(nm / 2)tMCLK
+ 20
ns Master mode
Start
condition
hold time
tHD;STA
SCL,
SDA
(
1 + nm / 2) tMCLK 20 (1 + nm)tMCLK + 20
ns
Master mode
Maximum value
is applied when
m, n = 1, 8.
Otherwise, the
minimum value is
applied.
Stop
condition
setup time
tSU;STO
SCL,
SDA
(1
+ nm / 2) tMCLK 20 (1 + nm / 2)tMCLK + 20 ns Master mode
Start
condition
setup time
tSU;STA
SCL,
SDA
(1
+ nm / 2)tMCLK 20 (1 + nm / 2)tMCLK + 20 ns Master mode
Bus free time
between
stop
condition
and start
condition
tBUF
SCL,
SDA
(2 nm
+ 4)tMCLK 20
—ns
Data hold
time
tHD;DAT
SCL,
SDA
3 tMCLK
20
ns Master mode
Data setup
time
tSU;DAT
SCL,
SDA
(
2 +nm / 2)tMCLK 20 (1 + nm / 2)tMCLK + 20 ns
Master mode
When assuming
that “L” of SCL is
not extended, the
minimum value is
applied to first bit
of continuous
data.
Otherwise, the
maximum value
is applied.
Setup time
between
clearing
interrupt and
SCL rising
tSU;INT
SCL
(nm / 2)tMCLK
20
(1
+ nm / 2)tMCLK + 20 ns
Minimum value is
applied to
interrupt at 9th
SCL
↓. Maximum
value is applied
to interrupt at 8th
SCL
↓.
SCL clock
“L” width
tLOW
SCL
4 tMCLK
20
ns At reception
SCL clock
“H” width
tHIGH
SCL
4 tMCLK
20
ns At reception
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