- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄45195 > MB95F124NBPF 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PQFP100 PDF資料下載
參數(shù)資料
| 型號(hào)： | MB95F124NBPF |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 55/80頁(yè) |
| 文件大?。?/td> | 1488K |
| 代理商： | MB95F124NBPF |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)當(dāng)前第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)
MB95120MB Series
59
(VCC
= 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = 40 °C to + 105 °C)
(Continued)
Parameter
Sym-
bol
Pin
name
Condition
Value*2
Unit
Remarks
Min
Max
SCL clock
“L” width
tLOW
SCL0
R
= 1.7 k,
C
= 50 pF*1
(2
+ nm / 2) tMCLK 20
ns
Master mode
SCL clock
“H” width
tHIGH
SCL0
(nm
/ 2) tMCLK 20
(nm
/ 2 ) tMCLK + 20
ns
Master mode
Start condition
hold time
tHD;STA
SCL0
SDA0
(
1 + nm / 2) tMCLK 20
(
1 + nm) tMCLK + 20
ns
Master mode
Maximum value is
applied when m,
n
= 1, 8.
Otherwise, the
minimum value is
applied.
Stop condition
setup time
tSU;STO
SCL0
SDA0
(1
+ nm / 2) tMCLK 20 (1 + nm / 2) tMCLK + 20
ns
Master mode
Start condition
setup time
tSU;STA
SCL0
SDA0
(1
+ nm / 2) tMCLK 20 (1 + nm / 2) tMCLK + 20
ns
Master mode
Bus free time
between stop
condition and
start condition
tBUF
SCL0
SDA0
(2 nm
+ 4) tMCLK 20
ns
Data hold time tHD;DAT
SCL0
SDA0
3 tMCLK
20
ns
Master mode
Data setup
time
tSU;DAT
SCL0
SDA0
(
2 + nm / 2) tMCLK 20 (1 + nm / 2) tMCLK + 20 ns
Master mode
When assuming
that “L” of SCL is
not extended, the
minimum value is
applied to first bit
of continuous
data.
Otherwise,
the maximum
value is applied.
Setup time
between
clearing
interrupt and
SCL rising
tSU;INT SCL0
(nm
/ 2) tMCLK 20
(1 + nm
/ 2) tMCLK + 20
ns
Minimum value is
applied to interrupt
at 9th SCL
↓.
Maximum value is
applied to interrupt
at 8th SCL
↓.
SCL clock “L”
width
tLOW
SCL0
4 tMCLK
20
ns
At reception
SCL clock “H”
width
tHIGH
SCL0
4 tMCLK
20
ns
At reception
Start condition
detection
tHD;STA
SCL0
SDA0
2 tMCLK
20
ns
Undetected when
1 tMCLK is used at
reception
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB95F124JBPMC | 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PQFP100 |
| MB95F124MBPMC | 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PQFP100 |
| MB95F134NSPFV | 8-BIT, FLASH, 32.5 MHz, MICROCONTROLLER, PDSO28 |
| MB95F136JWPFV | 8-BIT, FLASH, 32.5 MHz, MICROCONTROLLER, PDSO28 |
| MB95136MPFV | 8-BIT, MROM, 32.5 MHz, MICROCONTROLLER, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB95F124NBPMC | 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:8-bit Microcontrollers |
| MB95F126JB | 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:8-bit Microcontrollers |
| MB95F126JBPF | 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:8-bit Microcontrollers |
| MB95F126JBPF-GE1 | 制造商:FUJITSU 功能描述: 制造商:FUJITSU 功能描述:8BIT MCU 32K FLASH 1K RAM QFP100 制造商:FUJITSU 功能描述:8BIT MCU, 32K FLASH, 1K RAM, QFP100 |
| MB95F126JBPFR-GE1 | 制造商:FUJITSU 功能描述:MCU 8-BIT 8FX 32K FLASH QFP100 制造商:FUJITSU 功能描述:MCU, 8-BIT, 8FX, 32K FLASH, QFP100 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。