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參數(shù)資料
| 型號： | MB95F118AWPV |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQCC48 |
| 封裝： | PLASTIC, BCC-48 |
| 文件頁數(shù)： | 43/58頁 |
| 文件大小： | 629K |
| 代理商： | MB95F118AWPV |
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MB95110A Series
48
(Vcc
= 3.3 V, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
(Continued)
Parameter
Sym-
bol
I/O Timing
Unit
Remarks
Min
Max
SCL clock “L” width
tLOW
(2
+ nm*2 / 2)
MCLK*1
20
ns
Master mode
SCL clock “H” width
tHIGH
(nm*2
/ 2)
MCLK*1
20
(nm*2
/ 2 )
MCLK*1
+ 20
ns
Master mode
Start condition hold time
tHD;STA
(
1 + nm*2 / 2)
MCLK*1
20
(
1 + nm*2)
MCLK*1
+ 20
ns
Master mode
Maximum value is applied when
m, n
= 1, 8.
Otherwise, the minimum
value is applied.
Stop condition setup time
tSU;STO
(1
+ nm*2 / 2)
MCLK*1
20
(1
+ nm*2 / 2)
MCLK*1
+ 20
ns
Master mode
Start condition setup time
tSU;STA
(1
+ nm*2 / 2)
MCLK*1
20
(1
+ nm*2 / 2)
MCLK*1
+ 20
ns
Master mode
Bus free time between stop
condition and start condition
tBUF
(2 nm*2
+ 4)
MCLK*1
20
ns
Data hold time
tHD;DAT
3 MCLK*1
20
ns
Master mode
Data setup time
tSU;DAT
(
2 + nm*2 / 2)
MCLK*1
20
(
1 + nm*2 / 2)
MCLK*1
+ 20
ns
Master mode
When assuming that “L” of SCL
is not extended,
the minimum value is applied to
first bit of continuous data. Oth-
erwise, the maximum
value is applied.
Setup time between clearing
interrupt and SCL rising
tSU;INT
(nm*2
/ 2)
MCLK*1
20
/ 2)
MCLK*1
+ 20
ns
Minimum value is applied to in-
terrupt at 9th SCL
↓. Maximum
value is applied to interrupt at
8th SCL
↓.
SCL clock “L” width
tLOW
4 MCLK*1
20
ns
At reception
SCL clock “H” width
tHIGH
4 MCLK*1
20
ns
At reception
Start condition detection
tHD;STA
2 MCLK*1
20
ns
Undetected when 1 MCLK is
used at reception
Stop condition detection
tSU;STO
2 MCLK*1
20
ns
Undetected when 1 MCLK is
used at reception
Restart condition detection
condition
tSU;STA
2 MCLK*1
20
ns
Undetected when 1 MCLK is
used at reception
Bus free time
tBUF
2 MCLK*1
20
ns
At reception
Data hold time
tHD;DAT
2 MCLK*1
20
ns
At slave transmission mode
Data setup time
tSU;DAT
tLOW
3 MCLK*1
20
ns
At slave transmission mode
Data hold time
tHD;DAT
0
ns
At reception
Data setup time
tSU;DAT
MCLK*1
20
ns
At reception
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