參數(shù)資料
型號: MB95F108AJWPMC-GE1
廠商: Fujitsu Semiconductor America Inc
文件頁數(shù): 34/72頁
文件大小: 0K
描述: IC MCU 60K FLASH 64-LQFP
標(biāo)準(zhǔn)包裝: 1
系列: F²MC MB95100AM
核心處理器: F²MC-8FX
芯體尺寸: 8-位
速度: 16MHz
連通性: I²C,LIN,SIO,UART/USART
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 54
程序存儲器容量: 60KB(60K x 8)
程序存儲器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x8/10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 722 (CN2011-ZH PDF)
配用: 865-1104-ND - KIT STARTER 8FX MCU MB95F108AHS
其它名稱: 865-1070
MB95100AM Series
4
DS07-12614-5E
■ PRODUCT LINEUP
(Continued)
Part number
Parameter
MB95
108AM
MB95F
104AMS/
MB95F
106AMS/
MB95F
108AMS
MB95F
104ANS/
MB95F
106ANS/
MB95F
108ANS
MB95F
104AMW/
MB95F
106AMW/
MB95F
108AMW
MB95F
104ANW/
MB95F
106ANW/
MB95F
108ANW
MB95F
104AJS/
MB95F
106AJS/
MB95F
108AJS
MB95F
104AJW/
MB95F
106AJW/
MB95F
108AJW
Type
MASK
ROM
product
Flash memory product
ROM capacity*1
60 Kbytes (Max)
RAM capacity*1
2 Kbytes (Max)
Reset output
Yes
No
Op
tio
n*
2
Clock system
Selectable
single/dual
clock*3
Single clock
Dual clock
Single clock
Dual clock
Low voltage
detection reset
Yes/No
No
Yes
No
Yes
Clock supervisor
No
Yes
CPU functions
Number of basic instructions
: 136
Instruction bit length
: 8 bits
Instruction length
: 1 to 3 bytes
Data bit length
: 1, 8, and 16 bits
Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz)
Interrupt processing time
: 0.6
μs (at machine clock frequency 16.25 MHz)
General-pur-
pose I/O ports
Single clock product : 54 ports (N-ch open drain : 6 ports, CMOS : 48 ports)
Dual clock product : 52 ports (N-ch open drain : 6 ports, CMOS : 46 ports)
Programmable input voltage levels of port :
Automotive input level
/ CMOS input level / hysteresis input level
Timebase timer
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
Watchdog timer
Reset generated cycle
At main oscillation clock 10 MHz
: Min 105 ms
At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms
Wild register
Capable of replacing 3 bytes of ROM data
I2C
Master/slave sending and receiving
Bus error function and arbitration function
Detecting transmitting direction function
Start condition repeated generation and detection functions
Built-in wake-up function
UART/SIO
Data transfer capable in UART/SIO
Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate generator
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
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