參數(shù)資料
型號(hào)： MB91F482PMC-GE1
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 57/96頁
文件大?。?/td> 2461K
代理商： MB91F482PMC-GE1
MB91470/480 Series
60
DS07–16901–9E
(Continued)
*1 : INITX = “L” : Indicates the pin status with INITX remaining at the “L” level.
*2 : INITX = “H” : Indicates the pin status existing immediately after INITX transition from “L” to “H” level.
Pin name
Function
During initialization
In sleep mode
In stop mode
INITX
= “L”*1 INITX = “H”*2
HIZ
= 0HIZ = 1
PD0 to PD3
AN2-8
to
AN2-11
Output Hi-Z/
Input disabled
Output Hi-Z/
Input "0" fixed
Retention of the
immediately
prior state
Retention of the
immediately
prior state
Output Hi-Z/
Input “0” fixed
PE0 to PE3
AN3-0
to
AN3-3
PE4 to PE7
AN4-0
to
AN4-3
PF0
CLKPOUT
Output Hi-Z/
Input disabled
Output Hi-Z/
Input enabled
Retention of the
immediately
prior state
Retention of the
immediately
prior state
Output Hi-Z/
Input “0” fixed
PF1 to PF6
GPIO
PG0, PG3
SCK0, SCK1
Output Hi-Z/
Input disabled
Output Hi-Z/
Input enabled
Retention of the
immediately
prior state
Retention of the
immediately
prior state
Output Hi-Z/
Input “0” fixed
PG1, PG4
SIN0, SIN1
PG2, PG5
SOT0, SOT1
PH0, PH3
SCK2, SCK3
PH1, PH4
SIN2, SIN3
PH2, PH5
SOT2, SOT3
PJ0, PJ2,
PJ4, PJ6
TIN0 to TIN3
Output Hi-Z/
Input disabled
Output Hi-Z/
Input enabled
Retention of the
immediately
prior state
Retention of the
immediately
prior state
Output Hi-Z/
Input “0” fixed
PJ1, PJ3,
PJ5, PJ7
TOUT0
to
TOUT3
PL0
AIN0
Output Hi-Z/
Input disabled
Output Hi-Z/
Input enabled
Retention of the
immediately
prior state
Retention of the
immediately
prior state
Output Hi-Z/
Input “0” fixed
PL1
BIN0
PL2
ZIN0
PM0 to PM3
PPG0
to
PPG3
Output Hi-Z/
Input disabled
Output Hi-Z/
Input enabled
Retention of the
immediately
prior state
Retention of the
immediately
prior state
Output Hi-Z/
Input “0” fixed
PP0 to PP3
IC0 to IC3
Output Hi-Z/
Input disabled
Output Hi-Z/
Input enabled
Retention of the
immediately
prior state
Retention of the
immediately
prior state
Output Hi-Z/
Input “0” fixed
PP4
CKI0
PP5
DTTI0
PQ0 to PQ5
RTO0 to
RTO5
PR0 to PR3
IC4 to IC7
Output Hi-Z/
Input disabled
Output Hi-Z/
Input enabled
Retention of the
immediately
prior state
Retention of the
immediately
prior state
Output Hi-Z/
Input “0” fixed
PR4
CKI1
PR5
DTTI1
PS0 to PS5
RTO6
to
RTO11
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