參數(shù)資料
型號(hào): MB91F479BGL-GE1
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PBGA144
封裝: 12 X 12 MM, 1.45 MM HEIGHT, 0.80 MM PITCH, PLASTIC, FBGA-144
文件頁(yè)數(shù): 23/92頁(yè)
文件大?。?/td> 2431K
代理商: MB91F479BGL-GE1
MB91470/480 Series
DS07-16901-5E
3
(Continued)
12-bit A/D Converter (successive approximation type)
Resolution
: 12 bits
Conversion Time : 2.0 s (minimum conversion time for 33 MHz peripheral clock (CLKP))
2.2
s (minimum conversion time for 40 MHz peripheral clock (CLKP))
Differential input mode is available.
Clock monitor
Peripheral clock (CLKP) divided by 2/4/8/16/32/64/128/256 can be output.
Multiplication and Addition Calculator
RAM : Instruction RAM (I-RAM)
256
× 16-bit
Factor RAM (X-RAM)
64
× 32-bit
Variable RAM (Y-RAM)
64
× 32-bit
High-speed multiplication and addition (seven-stage pipeline processing)
Product addition (32-bit × 32-bit + 72-bit)
Operation result is extracted rounded from 72 bits to 32 bits or 72-bit result data reading.
DMAC (DMA Controller)
Transfers can be started by software or by interrupts from the built-in peripherals.
Wild register
Instructions or data located at a target address can be replaced (in the built-in Flash/ROM area only) .
External bus interface
Maximum operating frequency of 40 MHz
16-bit address full output (64 Kbytes space) capability
8/16-bit data output
Use of unused data/address pins as general-purpose I/O ports
Totally independent 3-area chip select outputs that can be set at minimum of 64 Kbytes.
Support of interface for various memory (SRAM, ROM/Flash)
Basic bus cycle : 2 cycles
Automatic wait cycle generator that can be programmed for each area and can insert waits
External wait cycle using RDY input
Other Features
Watchdog timer
Low-power consumption modes
Sleep/stop function
CMOS technologies : 0.18
m
Power supply : Single power supply (VCC
= 4.0 V to 5.5 V)
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