參數(shù)資料
型號： MB91F469TAPMC-GSE2
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-144
文件頁數(shù)： 127/140頁
文件大?。?/td> 4819K
代理商： MB91F469TAPMC-GSE2
MB91460T Series
DS705-00001-2v1-E
87
*1 : The
Interrupt Control Registers (ICRs) are located in the interrupt controller and set the interrupt level for
each interrupt request. An ICR is provided for each interrupt request.
*2 : The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the
table base register value (TBR) . The TBR specifies the top of the EIT vector table. The addresses listed in the
table are for the default TBR value (000FFC00H) . The TBR is initialized to this value by a reset. The TBR is set
to 000FFC00H after the internal boot ROM is executed.
*3 : D
MA Resource Number is the resource number used for DMA operation.
No number means that this resource interrupt cannot be used to trigger a DMA transfer.
*4 : ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03H : IOS[0]).
*5 : Used by REALOS
*6 : Memory Protection Unit (MPU) support
Low Voltage Detection
138
8A
ICR61
47DH
1D4H
000FFDD4
-
Reserved
139
8B
1D0H
000FFDD0
-
Timebase Overflow
140
8C
ICR62
47EH
1CCH
000FFDC
C
-
PLL Clock Gear
141
8D
1C8H
000FFDC8
-
DMA Controller
142
8E
ICR63
47FH
1C4H
000FFDC4
-
Main/Sub OSC stability
wait
143
8F
1C0H
000FFDC0
-
Security vector
144
90
-
1BCH
000FFDBC
-
Used by the INT
instruction
145
to
255
91
to
FF
--
1B8H
to
000H
000FFDB8
to
000FFC00
-
Interrupt
Interrupt number
Interrupt level *1
Interrupt vector *2
DMA *3
Resource
Number
Decimal
Hexa-
decimal
Setting
Register
address
Offset
Default
Vector
address
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