參數(shù)資料
型號(hào): MB91F313APMC-GE1
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP120
封裝: 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120
文件頁數(shù): 18/72頁
文件大?。?/td> 1843K
代理商: MB91F313APMC-GE1
MB91313A Series
DS07-16706-4E
25
2.
Internal architecture
The FR family of CPUs uses a Harvard architecture in which the instruction bus and data bus are separated.
A 32-bit
16-bit bus converter is connected to the 32-bit bus (F-bus) to provide an interface between the
CPU and peripheral resources.
A Harvard
Princeton bus converter is connected to both of the I-bus and D-bus, providing an interface
between the CPU and the bus controller.
D-bus
32
I-bus
Built-in
RAM
Built-in
ROM
F-bus
X-bus
32
R-bus
Address
Real Bus
FR-CPU
32-bit
16-bit
bus converter
Peripheral resource, port
Bus controller
16
32
24
16
Harvard
Princeton
bus converter
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