參數(shù)資料
型號： MB91F264BPFV-G-E1
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP100
封裝： PLASTIC, LQFP-100
文件頁數(shù)： 13/60頁
文件大小： 720K
代理商： MB91F264BPFV-G-E1
MB91260B Series
20
Clock control block
Take the oscillation stabilization wait time during Low level input to the INIT pin.
Switch shared port function
To switch between the use as a port and the use as a dedicated pin, use the port function register (PFR).
Low Power Consumption Mode
(1) To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR:
or time-base counter control register) and be sure to use the following seaquence
In addition, please set I flag, ILM, and ICR to diverge to the interruption handler that is the return factor after
the standby returns.
(2) Please do not do the following when the monitor debugger is used.
Break point setting for above instruction lines
Step execution for above instruction lines
Notes on the PS register
As the PS register is processed by some instructions in advance, exception handling below may cause the
interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register
to be updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it
performs operations before and after the EIT as specified in either case.
1. The following operations are performed when the instruction followed by a DIV0U/DIV0S instruction results
in : (a) acceptance of a user interrupt or NMI, (b) step execution, or (c) a break at a data event or emulator menu.
(1) The D0 and D1 flags are updated in advance.
(2) An EIT handling routine (user interrupt, NMI, or emulator) is executed.
(3) Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are
updated to the same values as in (1).
2. The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed
to enable interruptions when a user interrupt or NMI trigger even has occurred.
(1) The PS register is updated in advance.
(2) An EIT handling routine (user interrupt, NMI) is executed.
(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
same value as in (1).
(LDI
#value_of_standby, R0)
: Value_of standby is write data to STCR.
(LDI
#_STCR, R12)
: _STCR is address (481H) of STCR.
STB
R0, @R12
: Writing to standby control register (STCR)
LDUB
@R12, R0
: STCR read for synchronous standby
LDUB
@R12, R0
: Dummy re-read of STCR
NOP
: NOP
× 5 for arrangement of timing
NOP
相關(guān)PDF資料
PDF描述
MB91264BPFV-G-XXX 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP100
MB91F264BPFV-GE1 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP100
MB91F264BPF-G 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP100
MB91264BPMC-G-XXXE1 RISC MICROCONTROLLER, PQFP100
MB91F264BPF-GE1 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP100
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