參數(shù)資料
型號: MB91F133PBT
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-Bit RISC Microcontroller
中文描述: 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PBGA144
封裝: PLASTIC, FBGA-144
文件頁數(shù): 105/123頁
文件大?。?/td> 1362K
代理商: MB91F133PBT
MB91133/MB91F133
105
I
INSTRUCTIONS (165 INSTRUCTIONS)
1.
How to Read Instruction Set Summary
(1) Names of instructions
Instructions marked with * are not included in CPU specifications. These are extended instruction codes
added/extended at assembly language levels.
(2) Addressing modes specified as operands are listed in symbols.
Refer to “2. Addressing mode symbols” for further information.
(3) Instruction types
(4) Hexa-decimal expressions of instructions
(5) The number of machine cycles needed for execution
a: Memory access cycle and it has possibility of delay by Ready function.
b: Memory access cycle and it has possibility of delay by Ready function.
If an object register in a LD operation is referenced by an immediately following instruction, the interlock
function is activated and number of cycles needed for execution increases.
c: If an immediately following instruction operates to an object of R15, SSP or USP in read/write mode or
if the instruction belongs to instruction format A group, the interlock function is activated and number of
cycles needed for execution increases by 1 to make the total number of 2 cycles needed.
d: If an immediately following instruction refers to MDH/MDL, the interlock function is activated and number
of cycles needed for execution increases by 1 to make the total number of 2 cycles needed.
For a, b, c and d, minimum execution cycle is 1.
(6) Change in flag sign
Flag change
C : Change
– : No change
0 : Clear
1 : Set
Flag meanings
N : Negative flag
Z : Zero flag
V : Over flag
C : Carry flag
(7) Operation carried out by instruction
Mnemonic
ADD
Rj,
* ADD
Type
A
C
,
,
(3)
OP
A6
A4
,
,
(4)
CYC
1
1
,
,
(5)
NZVC
CCCC
CCCC
,
,
(6)
Operation
Ri + Rj
Ri
Ri + s5
Ri
,
,
(7)
Remarks
Ri
Ri
#s5,
,
,
(1)
(2)
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