參數(shù)資料
型號: MB91133PMT2-XXX
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP144
封裝: PLASTIC, LQFP-144
文件頁數(shù): 77/112頁
文件大?。?/td> 508K
代理商: MB91133PMT2-XXX
MB91133/MB91F133A
67
Block Diagram
IM
INT0
OR
NMI
RI00
RI47
(DLYIRQ)
DLYI
4
5
Priority grade judgement
6
HLDREQ
(Holding
request)
Generation
of
LEVEL /
VECTOR
judgement
LEVEL4 to 0
HLDCAN
VCT5 to 0
ICR00
LEVEL
judgement
NMI processing
ICR47
R-BUS
Note : DLYI shown in the figure indicates delay interruption area. (Refer to the chapter on the delay interruption
module for details.)
INTO is the wake-up signal to the clock control area in case of sleep or stop.
HLDCAN is the bus vacation request signal to bus masters other than the CPU.
There is no NMI function in this model.
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