參數(shù)資料
型號: MB91133PMC-XXX
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù): 101/116頁
文件大小: 2730K
代理商: MB91133PMC-XXX
MB91130 Series
DS07-16308-3E
85
17. FLASH Memory
The MB91130 series have a 254-KB (2 Mbit) capacity and feature a FLASH memory that can write each half-
word (16 bits) using the FR-CPU, delete individual sectors sector and delete groups of sectors together using
a single 3-V power source.
Outline of FLASH Memory
This is a built-in 3-V 254-KB FLASH memory. This FLASH memory is the same as our 2-Mbit (256 K
× 8 / 128
K
× 16) FLASH memory MBM29LV400C and writing is possible from outside the device using a ROM writer. If
used as a built-in ROM of the FR-CPU, as well as having an equivalent function to the MBM29LV400C, instruc-
tions
/ data can be read per word (32 bits) and high-speed operation of the device can be realized.
Refer to the MBM29LV400C data sheet as well as this manual.
The following functions can be realised in MB91130 series by combining the FLASH memory macro and FR-
CPU interface circuits.
Functioning as memory for CPU program
/ data storage
Access is possible with 32-bit bus width when used as ROM
Reading
/ writing and erasing (automatic program algorithm *) are possible using CPU
MBM29LV400C-equivalent function of single FLASH memory products
Reading
/ writing and erasing (automatic program algorithm *) are possible using ROM writer
A case where this FLASH memory is used from FR-CPU is described in this section.
Refer to the ROM writer manual separately for details if this FLASH memory is used from ROM writer.
* : Automatic program algorithm
= Embedded Algorithm
Block Diagram
RDY/BUSY
RESET
BYTE
OE
WE
CE
FA18 - 0
Address buffer
Data buffer
CA18 - 0
Interruption
request
Bus
control
signal
INTE
RDYINT
RDY
WE
FR-C bus (instruction / data)
Rising edge detection
Control signal
generation
CD31 - 0
DI15 - 0
FLASH memory
2 Mbit (254 K
× 8/127 K × 16)
DO31 - 0
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