MB91133/MB91F133
2
(Continued)
2.
Bus Interface
24-bit address output, 8/16-bit data input/output
Basic bus cycle : 2 clock cycles
Interface support for various memories
Unused data and address pins can be used as input/output ports.
Supports “l(fā)ittle endian” mode
3.
Built-in ROM
Mask device : 254 KB; FLASH device : 254 KB; EVA-FLASH device : 254 KB
Built-in RAM
4.
Mask device : 8 KB; FLASH device : 8 KB; EVA-FLASH device : 8 KB
DMA Controller
5.
This is a descriptor-type MA controller whose transfer parameters are arranged in the main memory.
A maximum of 8 factors in total (internal and external) can be transferred.
External factors are 3 channels.
Bit Search Module
6.
Searches the first “1” / “0” change bit positions within 1 cycle from MSB in 1 word
Timer
16-bit reload timer
×
5 channels
16-bit OCU
×
8 channels, ICU
×
4 channels, free-run timer
×
1 channel
Output waveform adjusting function for AC motor waveforms is included in the above timer.
8/16-bit up/down timer/counter (8-bit
×
2 channels or 16-bit
×
1 channel)
External interruption and pin are shared for AIN and BIN.
16-bit down count timer
×
5 channels; can also be used as the UART baud rate timer
16-bit PPG timer
×
6 channels; out-pulse cycle / duty can be changed at random
D/A Converter
8-bit
×
3 channels
A/D Converter (Sequential comparison type)
10-bit
×
8 channels
Sequential conversion method (conversion time 5.0
μ
s at 33 MHz)
Setting for single conversion, scan conversion and repeat conversion is possible.
Conversion starting function using hardware or software
7.
8.
9.
10. Serial I/O
UART
×
5 channels; clock synchronous serial transfer with LSB / MSB switching function is possible for both.
Serial data output or serial lock output can be selected using push-pull / open-drain software.
11. Level Comparator Input
1 channel; shared input and pins of A/D converter.
12. Clock Switching Function
Base clock : Software can be used to select from two types of clock sources, namely 32 kHz and high-speed.
Gear function : Four types of settings (1 : 1, 1 : 2, 1 : 4, 1 : 8) can be set individually as the operating clock
ratio to the basic clock per CPU and peripheral equipment.