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參數(shù)資料
| 型號： | MB91133 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 32-Bit RISC Microcontroller |
| 中文描述： | 32位RISC微控制器 |
| 文件頁數(shù)： | 115/123頁 |
| 文件大小： | 1362K |
| 代理商： | MB91133 |
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MB91133/MB91F133
115
Other instructions (16 instructions)
*1: In the ADDSP instruction, the reference between u8 of TYPE-D in the instruction format and assembler
description s10 is as follows.
s10
→
s8 = s10>>2
*2: In the ENTER instruction, the reference between i8 of TYPE-C in the instruction format and assembler
description u10 is as follows.
u10
→
u8 = u10>>2
*3: If either of R0 to R7 is specified in reglist, assembler generates LDM0. If either of R8 to R15 is specified,
assembler generates LDM1. Both LDM0 and LDM1 may be generated.
*4: The number of cycles needed for execution of LDM0 (reglist) and LDM1 (reglist) is given by the following
calculation; a
×
(n – 1) + b + 1 when “n” is number of registers specified.
*5: If either of R0 to R7 is specified in reglist, assembler generates STM0. If either of R8 to R15 is specified,
assembler generates STM1. Both STM0 and STM1 may be generated.
*6: The number of cycles needed for execution of STM0 (reglist) and STM1 (reglist) is given by the following
calculation; a
×
n + 1 when “n” is number of registers specified.
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
NOP
E
9F – A
1
– – – – No changes
ANDCCR #u8
ORCCR
#u8
D
D
83
93
c
c
C C C C
C C C C
CCR and u8
→
CCR
CCR or u8
→
CCR
– – – – i8
→
ILM
STILM
#u8
D
87
1
Set ILM immediate
value
ADDSP
#s10
*
1
D
A3
1
– – – – R15 + = s10
ADD SP instruction
EXTSB
EXTUB
EXTSH
EXTUH
Ri
Ri
Ri
Ri
E
E
E
E
97 – 8
97 – 9
97 – A
97 – B
1
1
1
1
– – – –
– – – –
– – – –
– – – –
Sign extension 8
→
32 bits
Zero extension 8
→
32 bits
Sign extension 16
→
32 bits
Zero extension 16
→
32 bits
(R15)
→
reglist,
R15 increment
(R15)
→
reglist,
R15 increment
(R15 + +)
→
reglist,
LDM0
(reglist)
LDM1
(reglist)
* LDM
(reglist)
*
3
D
D
8C
8D
*
4
*
4
–
– – – –
– – – –
– – – –
Load-multi R0 to R7
Load-multi R8 to R15
Load-multi R0 to R15
STM0
(reglist)
STM1
(reglist)
* STM2
(reglist)
*
5
D
D
8E
8F
*
6
*
6
–
– – – –
– – – –
– – – –
R15 decrement,
reglist
→
(R15)
R15 decrement,
reglist
→
(R15)
reglist
→
(R15 + +)
Store-multi R0 to R7
Store-multi R8 to R15
Store-multi R0 to R15
ENTER
#u10
*
2
D
0F
1+a
– – – – R14
→
(R15 – 4),
R15 – 4
→
R14,
R15 – u10
→
R15
– – – – R14 + 4
→
R15,
(R15 – 4)
→
R14
– – – – Ri
→
TEMP
(Rj)
→
Ri,
TEMP
→
(Rj)
Entrance processing
of function
LEAVE
E
9F – 9
b
Exit processing of
function
XCHB
@Rj, Ri
A
8A
2a
For SEMAFO
management
Byte data
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