參數(shù)資料
型號(hào)： MB90P553APF
元件分類： 微控制器/微處理器
英文描述： 16-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 41/61頁(yè)
文件大小： 687K
代理商： MB90P553APF
MB90550A/550B Series
46
(13) I2C Interface
(VCC
= 5.0 V±10%, VSS = AVSS = 0.0 V, TA = 40 °C to +85 °C)
Notes: “m” and“n” in the above table represent the values of shift clock frequency setting bits (CS4 to CS0) in the
clock control register “ICCR”. For details, refer to the register description in the hardware manual.
tDOSUO represents the minimum value when the interrupt period is equal to or greater than the SCL “L” width.
The SDA and SCL output values indicate that that rise time is 0 ns.
Parameter
Symbol
Pin name
Value
Unit
Remarks
Min
Max
Internal clock cycle time
tCP
—
62.5
666
ns
All products
Start condition output
tSTAO
SDA0 to SDA2
SCL0 toSCL2
tCP
× m × n/2 – 20 tCP × m × n/2 + 20 ns
Only as master
Stop condition output
tSTOO
tCP (m
× n/2 + 4)
– 20
tCP (m
× n/2 + 4)
+ 20
ns
Start condition detection
tSTAI
3 tCP + 40
—
ns
Only as slave
Stop condition detection
tSTOI
3 tCP + 40
—
ns
SCL output “L” width
tLOWO
SCL0 to SCL2
tCP
× m × n/2 – 20 tCP × m × n/2 + 20 ns
Only as master
SCL output “H” width
tHIGHO
tCP (m
× n/2 + 4)
– 20
tCP (m
× n/2 + 4)
+ 20
ns
SDA output delay time
tDOO
SDA0 to SDA2
SCL0 to SCL2
2 tCP – 20
2 tCP + 20
ns
Setup after SDA output
interrupt period
tDOSUO
4 tCP – 20
—
ns
SCL input “L” width
tLOWI
SCL0 to SCL2
3 tCP + 40
—
ns
SCL input “H” width
tHIGHI
tCP + 40
—
ns
SDA input setup time
tSUI
SDA0 to SDA2
SCL0 to SCL2
40
—
ns
SDA input hold time
tHOI
0—
ns
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