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參數(shù)資料
| 型號(hào)： | MB90F884BHSPF |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 37/80頁(yè) |
| 文件大?。?/td> | 2171K |
| 代理商： | MB90F884BHSPF |
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MB90880 Series
42
DS07-13743-5E
(Continued)
× : The interrupt request flag is not cleared by the interrupt clear signal.
: The interrupt request flag is cleared by the interrupt clear signal.
: The interrupt request flag is cleared by the interrupt clear signal. Stop request function provided at receiving
only.
* : Flash writing/deletion, the time base timer and watch timer cannot be used simultaneously.
Note : If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are
cleared by the EI2OS/
μDMAC interrupt clear signal. Therefore, when either of the two sources for the EI2OS/
μDMAC function is used, the other interrupt function can not be used. In this case, set the interrupt request
enable bit to “0” in the appropriate resource and take measures by software polling.
Interrupt source
Clearing
of EI2OS
μDMAC
channel
no.
Interrupt vector
Interrupt control
register
No.
Address
No.
Address
Multi-function serial ch.3 reception / status
#39
FFFF60H
ICR14
0000BEH
Multi-function serial ch.3 transmission
#40
FFFF5CH
Flash writing/deletion, time base timer, watch
timer*
×
#41
FFFF58H
ICR15
0000BFH
Delayed interrupt generation module
×
#42
FFFF54H
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