參數(shù)資料
型號： MB90F867EPMC
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 49/72頁
文件大?。?/td> 2203K
代理商： MB90F867EPMC
MB90860E Series
DS07-13748-5E
53
Bit setting: ESCR:SCES = 1, ECCR:SCDE = 0
(TA
= 40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Notes :
CL is load capacity value of pins when testing.
tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
Parameter
Symbol
Pin
Condition
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK0 to SCK3
Internal shift clock
mode output pins are
CL
= 80 pF + 1 TTL.
5 tCP
ns
SCK
↑ → SOT delay time
tSHOVI
SCK0 to SCK3
SOT0 to SOT3
50
+50
ns
Valid SIN
→ SCK ↓
tIVSLI
SCK0 to SCK3
SIN0 to SIN3
tCP + 80
ns
SCK
↓ → Valid SIN hold time
tSLIXI
SCK0 to SCK3
SIN0 to SIN3
0
ns
Serial clock “H” pulse width
tSHSL
SCK0 to SCK3
External shift clock
mode output pins are
CL
= 80 pF + 1 TTL.
3 tCP - tR
ns
Serial clock “L” pulse width
tSLSH
SCK0 to SCK3
tCP + 10
ns
SCK
↑ → SOT delay time
tSHOVE
SCK0 to SCK3
SOT0 to SOT3
2 tCP + 60
ns
Valid SIN
→ SCK ↓
tIVSLE
SCK0 to SCK3
SIN0 to SIN3
30
ns
SCK
↓ → Valid SIN hold time
tSLIXE
SCK0 to SCK3
SIN0 to SIN3
tCP + 30
ns
SCK fall time
tF
SCK0 to SCK3
10
ns
SCK rise time
tR
SCK0 to SCK3
10
ns
External Shift Clock Mode
SCK0 to SCK3
VIH
VIL
SOT0 to SOT3
0.8 V
2.4 V
tSLOVE
SIN0 to SIN3
VIL
VIH
VIL
VIH
VIL
tR
tF
tSHSL
tSLSH
tIVSHE
tSHIXE
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